val &= ~8; /* pass FIQs through */
val |= 2; /* enableNS */
writel(val, base + GIC_CPU_CTRL);
+ tegra_legacy_select_fiq(irq, true);
tegra_legacy_unmask_irq(irq);
}
void tegra_fiq_disable(int irq)
{
tegra_legacy_mask_irq(irq);
-}
-
-void tegra_fiq_select(int irq, int on)
-{
- tegra_legacy_select_fiq(irq, !!on);
+ tegra_legacy_select_fiq(irq, false);
}
#ifndef __ASM_ARCH_TEGRA_FIQ_H
#define __ASM_ARCH_TEGRA_FIQ_H
-/* change an interrupt to be an FIQ instead of an IRQ */
-void tegra_fiq_select(int n, int on);
-
/* enable/disable an interrupt that is an FIQ (safe from FIQ context?) */
void tegra_fiq_enable(int n);
void tegra_fiq_disable(int n);
-/* install an FIQ handler */
-int tegra_fiq_set_handler(void (*func)(void *data, void *regs, void *svc_sp),
- void *data);
-
#endif