[Sparc] Add support for decoding 'swap' instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203424 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp b/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp
index df2d3798a24206600e47e9481770de7e198bd210..5cd99d6bfe091c88154c39478154dea9672701b2 100644 (file)
--- a/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp
+++ b/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp
@@ -211,6 +211,8 @@ static DecodeStatus DecodeJMPL(MCInst &Inst, unsigned insn, uint64_t Address,
                                const void *Decoder);
 static DecodeStatus DecodeReturn(MCInst &MI, unsigned insn, uint64_t Address,
                                  const void *Decoder);
+static DecodeStatus DecodeSWAP(MCInst &Inst, unsigned insn, uint64_t Address,
+                               const void *Decoder);
 
 #include "SparcGenDisassemblerTables.inc"
 
@@ -445,3 +447,37 @@ static DecodeStatus DecodeReturn(MCInst &MI, unsigned insn, uint64_t Address,
   }
   return MCDisassembler::Success;
 }
+
+static DecodeStatus DecodeSWAP(MCInst &MI, unsigned insn, uint64_t Address,
+                               const void *Decoder) {
+
+  unsigned rd = fieldFromInstruction(insn, 25, 5);
+  unsigned rs1 = fieldFromInstruction(insn, 14, 5);
+  unsigned isImm = fieldFromInstruction(insn, 13, 1);
+  unsigned rs2 = 0;
+  unsigned simm13 = 0;
+  if (isImm)
+    simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
+  else
+    rs2 = fieldFromInstruction(insn, 0, 5);
+
+  // Decode RD.
+  DecodeStatus status = DecodeIntRegsRegisterClass(MI, rd, Address, Decoder);
+  if (status != MCDisassembler::Success)
+    return status;
+
+  // Decode RS1.
+  status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder);
+  if (status != MCDisassembler::Success)
+    return status;
+
+  // Decode RS1 | SIMM13.
+  if (isImm)
+    MI.addOperand(MCOperand::CreateImm(simm13));
+  else {
+    status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
+    if (status != MCDisassembler::Success)
+      return status;
+  }
+  return MCDisassembler::Success;
+}

diff --git a/lib/Target/Sparc/SparcInstrInfo.td b/lib/Target/Sparc/SparcInstrInfo.td
index fe3227e26b850ac0fe1e5647a925916c06a52d12..960261ce98357a502c7634b58eeac3f9cff6b8f6 100644 (file)
--- a/lib/Target/Sparc/SparcInstrInfo.td
+++ b/lib/Target/Sparc/SparcInstrInfo.td
@@ -1107,7 +1107,7 @@ let Predicates = [HasV9], hasSideEffects = 1, rd = 0, rs1 = 0b01111 in
  def MEMBARi : F3_2<2, 0b101000, (outs), (ins simm13Op:$simm13),
                     "membar $simm13", []>;
 
-let Constraints = "$val = $dst" in {
+let Constraints = "$val = $dst", DecoderMethod = "DecodeSWAP" in {
   def SWAPrr : F3_1<3, 0b001111,
                  (outs IntRegs:$dst), (ins MEMrr:$addr, IntRegs:$val),
                  "swap [$addr], $dst",

diff --git a/test/MC/Disassembler/Sparc/sparc-mem.txt b/test/MC/Disassembler/Sparc/sparc-mem.txt
index 37222476415739acc30dfcdc4658911ba3ef792a..6ad4be167214a4d211094efd83e70abd33981740 100644 (file)
--- a/test/MC/Disassembler/Sparc/sparc-mem.txt
+++ b/test/MC/Disassembler/Sparc/sparc-mem.txt
@@ -152,3 +152,12 @@
 
 # CHECK:      stx %o2, [%g1]
 0xd4 0x70 0x60 0x00
+
+# CHECK:     swap [%i0+%l6], %o2
+0xd4 0x7e 0x00 0x16
+
+# CHECK:     swap [%i0+32], %o2
+0xd4 0x7e 0x20 0x20
+
+# CHECK:     swap [%g1], %o2
+0xd4 0x78 0x60 0x00