12, 13, 14, 15, 16, 17, 27, 41
);
+DEF_FMT_TRANS_TBL(vpu_avsd,
+ 12, 13, 14, 15, 16, 17, 40, 41, 45
+);
+
DEF_FMT_TRANS_TBL(vpu_defaultd,
12, 13, 14, 15, 16, 17, 40, 41
);
5, 6, 7, 8, 9, 10, 11, 12, 13, 51
);
-const struct vpu_trans_info trans_vpu[FMT_TYPE_BUTT] = {
- SETUP_FMT_TBL(FMT_JPEGD , vpu_jpegd),
- SETUP_FMT_TBL(FMT_H263D , vpu_defaultd),
- SETUP_FMT_TBL(FMT_H264D , vpu_h264d),
+static const struct vpu_trans_info trans_vpu[FMT_TYPE_BUTT] = {
+ SETUP_FMT_TBL(FMT_JPEGD, vpu_jpegd),
+ SETUP_FMT_TBL(FMT_H263D, vpu_defaultd),
+ SETUP_FMT_TBL(FMT_H264D, vpu_h264d),
EMPTY_FMT_TBL(FMT_H265D),
SETUP_FMT_TBL(FMT_MPEG1D, vpu_defaultd),
SETUP_FMT_TBL(FMT_MPEG2D, vpu_defaultd),
SETUP_FMT_TBL(FMT_MPEG4D, vpu_defaultd),
- SETUP_FMT_TBL(FMT_VP6D , vpu_vp6d),
- SETUP_FMT_TBL(FMT_VP7D , vpu_defaultd),
- SETUP_FMT_TBL(FMT_VP8D , vpu_vp8d),
+ SETUP_FMT_TBL(FMT_VP6D, vpu_vp6d),
+ SETUP_FMT_TBL(FMT_VP7D, vpu_defaultd),
+ SETUP_FMT_TBL(FMT_VP8D, vpu_vp8d),
EMPTY_FMT_TBL(FMT_VP9D),
- SETUP_FMT_TBL(FMT_VC1D , vpu_vc1d),
- SETUP_FMT_TBL(FMT_AVSD , vpu_defaultd),
+ SETUP_FMT_TBL(FMT_VC1D, vpu_vc1d),
+ SETUP_FMT_TBL(FMT_AVSD, vpu_avsd),
- SETUP_FMT_TBL(FMT_PP , vpu_default_pp),
+ SETUP_FMT_TBL(FMT_PP, vpu_default_pp),
- SETUP_FMT_TBL(FMT_JPEGE , vpu_defaulte),
- SETUP_FMT_TBL(FMT_H264E , vpu_defaulte),
- SETUP_FMT_TBL(FMT_VP8E , vpu_vp8e),
+ SETUP_FMT_TBL(FMT_JPEGE, vpu_defaulte),
+ SETUP_FMT_TBL(FMT_H264E, vpu_defaulte),
+ SETUP_FMT_TBL(FMT_VP8E, vpu_vp8e),
};
#endif