ibm_newemac: PowerPC 440GX EMAC PHY clock workaround
authorValentine Barshak <vbarshak@ru.mvista.com>
Tue, 22 Apr 2008 00:46:46 +0000 (10:46 +1000)
committerJeff Garzik <jgarzik@redhat.com>
Fri, 25 Apr 2008 06:08:07 +0000 (02:08 -0400)
The PowerPC 440GX Taishan board fails to reset EMAC3 (reset timeout
error) if there's no link. Because of that it fails to find PHY
chip. The older ibm_emac driver had a workaround for that: the
EMAC_CLK_INTERNAL/EMAC_CLK_EXTERNAL macros, which toggle the Ethernet
Clock Select bit in the SDR0_MFR register. This patch does the same for
"ibm,emac-440gx" compatible chips. The workaround forces clock on -all-
EMACs, so we select clock under global emac_phy_map_lock.

BenH: Made that #ifdef CONFIG_PPC_DCR_NATIVE for now as dcri_* stuff
doesn't exist for MMIO type DCRs like Cell. Some future rework &
improvements of the DCR infrastructure will make that cleaner but
for now, this makes it work.

Signed-off-by: Valentine Barshak <vbarshak@ru.mvista.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
drivers/net/ibm_newemac/core.c
drivers/net/ibm_newemac/core.h

index 7c66727359d46ab29a817ac241fb15b14d6343da..4176dd6a2e83f2e1f964e68f36ee6e388c541bb2 100644 (file)
@@ -43,6 +43,8 @@
 #include <asm/io.h>
 #include <asm/dma.h>
 #include <asm/uaccess.h>
+#include <asm/dcr.h>
+#include <asm/dcr-regs.h>
 
 #include "core.h"
 
@@ -2333,6 +2335,11 @@ static int __devinit emac_init_phy(struct emac_instance *dev)
        dev->phy.mdio_read = emac_mdio_read;
        dev->phy.mdio_write = emac_mdio_write;
 
+       /* Enable internal clock source */
+#ifdef CONFIG_PPC_DCR_NATIVE
+       if (emac_has_feature(dev, EMAC_FTR_440GX_PHY_CLK_FIX))
+               dcri_clrset(SDR0, SDR0_MFR, 0, SDR0_MFR_ECS);
+#endif
        /* Configure EMAC with defaults so we can at least use MDIO
         * This is needed mostly for 440GX
         */
@@ -2365,6 +2372,12 @@ static int __devinit emac_init_phy(struct emac_instance *dev)
                        if (!emac_mii_phy_probe(&dev->phy, i))
                                break;
                }
+
+       /* Enable external clock source */
+#ifdef CONFIG_PPC_DCR_NATIVE
+       if (emac_has_feature(dev, EMAC_FTR_440GX_PHY_CLK_FIX))
+               dcri_clrset(SDR0, SDR0_MFR, SDR0_MFR_ECS, 0);
+#endif
        mutex_unlock(&emac_phy_map_lock);
        if (i == 0x20) {
                printk(KERN_WARNING "%s: can't find PHY!\n", np->full_name);
@@ -2490,8 +2503,11 @@ static int __devinit emac_init_config(struct emac_instance *dev)
        }
 
        /* Check EMAC version */
-       if (of_device_is_compatible(np, "ibm,emac4"))
+       if (of_device_is_compatible(np, "ibm,emac4")) {
                dev->features |= EMAC_FTR_EMAC4;
+               if (of_device_is_compatible(np, "ibm,emac-440gx"))
+                       dev->features |= EMAC_FTR_440GX_PHY_CLK_FIX;
+       }
 
        /* Fixup some feature bits based on the device tree */
        if (of_get_property(np, "has-inverted-stacr-oc", NULL))
index 4e74d8287c65b91d25a6a95ff36de8a0d2d16a6b..96ec48266b4a79238a475397c18327822638e5ed 100644 (file)
@@ -301,6 +301,10 @@ struct emac_instance {
  * Set if we have new type STACR with STAOPC
  */
 #define EMAC_FTR_HAS_NEW_STACR         0x00000040
+/*
+ * Set if we need phy clock workaround for 440gx
+ */
+#define EMAC_FTR_440GX_PHY_CLK_FIX     0x00000080
 
 
 /* Right now, we don't quite handle the always/possible masks on the
@@ -312,8 +316,8 @@ enum {
 
        EMAC_FTRS_POSSIBLE      =
 #ifdef CONFIG_IBM_NEW_EMAC_EMAC4
-           EMAC_FTR_EMAC4      | EMAC_FTR_HAS_NEW_STACR        |
-           EMAC_FTR_STACR_OC_INVERT    |
+           EMAC_FTR_EMAC4 | EMAC_FTR_HAS_NEW_STACR |
+           EMAC_FTR_STACR_OC_INVERT | EMAC_FTR_440GX_PHY_CLK_FIX |
 #endif
 #ifdef CONFIG_IBM_NEW_EMAC_TAH
            EMAC_FTR_HAS_TAH    |