[AArch64] Improve the readability of the ld/st optimization pass. NFC.

In this context, MI is an add/sub instruction not a loads/store.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@248540 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp b/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
index d37751449cc61f2b5261d00cbbb3a9c12a35d471..783a610ce0c3942de581d13e4172b0ea4f220907 100644 (file)
--- a/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
+++ b/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
@@ -750,10 +750,10 @@ static bool isMatchingUpdateInsn(MachineInstr *MI, unsigned BaseReg,
       break;
     // If the instruction has the base register as source and dest and the
     // immediate will fit in a signed 9-bit integer, then we have a match.
-    if (getLdStRegOp(MI).getReg() == BaseReg &&
-        getLdStBaseOp(MI).getReg() == BaseReg &&
-        getLdStOffsetOp(MI).getImm() <= 255 &&
-        getLdStOffsetOp(MI).getImm() >= -256) {
+    if (MI->getOperand(0).getReg() == BaseReg &&
+        MI->getOperand(1).getReg() == BaseReg &&
+        MI->getOperand(2).getImm() <= 255 &&
+        MI->getOperand(2).getImm() >= -256) {
       // If we have a non-zero Offset, we check that it matches the amount
       // we're adding to the register.
       if (!Offset || Offset == MI->getOperand(2).getImm())