ARM vqdmulh assembly parsing for the lane index operand.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142386 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMInstrNEON.td b/lib/Target/ARM/ARMInstrNEON.td
index e022f03cf006578ba08c9b11e448d627a7c569b7..96d8f7bf434378764ea0a06ff20a4e3d67f79bdb 100644 (file)
--- a/lib/Target/ARM/ARMInstrNEON.td
+++ b/lib/Target/ARM/ARMInstrNEON.td
@@ -2009,8 +2009,8 @@ class N3VDInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
 class N3VDIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
                 string OpcodeStr, string Dt, ValueType Ty, Intrinsic IntOp>
   : N3VLane32<0, 1, op21_20, op11_8, 1, 0,
-        (outs DPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
-        NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
+        (outs DPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
+        NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
         [(set (Ty DPR:$Vd),
               (Ty (IntOp (Ty DPR:$Vn),
                          (Ty (NEONvduplane (Ty DPR_VFP2:$Vm),
@@ -2020,8 +2020,8 @@ class N3VDIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
 class N3VDIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
                   string OpcodeStr, string Dt, ValueType Ty, Intrinsic IntOp>
   : N3VLane16<0, 1, op21_20, op11_8, 1, 0,
-        (outs DPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
-        NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
+        (outs DPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
+        NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
         [(set (Ty DPR:$Vd),
               (Ty (IntOp (Ty DPR:$Vn),
                          (Ty (NEONvduplane (Ty DPR_8:$Vm), imm:$lane)))))]> {

diff --git a/test/MC/ARM/neont2-mul-encoding.s b/test/MC/ARM/neont2-mul-encoding.s
index 8ad8cde9cd831556b161f5605edeac5605512ece..8f8fd5928ca1442f028dc663a1fb316f2343a382 100644 (file)
--- a/test/MC/ARM/neont2-mul-encoding.s
+++ b/test/MC/ARM/neont2-mul-encoding.s
@@ -31,13 +31,13 @@
        vqdmulh.s32     d16, d16, d17
        vqdmulh.s16     q8, q8, q9
        vqdmulh.s32     q8, q8, q9
-@      vqdmulh.s16     d11, d2, d3[0]
+       vqdmulh.s16     d11, d2, d3[0]
 
 @ CHECK: vqdmulh.s16   d16, d16, d17   @ encoding: [0x50,0xef,0xa1,0x0b]
 @ CHECK: vqdmulh.s32   d16, d16, d17   @ encoding: [0x60,0xef,0xa1,0x0b]
 @ CHECK: vqdmulh.s16   q8, q8, q9      @ encoding: [0x50,0xef,0xe2,0x0b]
 @ CHECK: vqdmulh.s32   q8, q8, q9      @ encoding: [0x60,0xef,0xe2,0x0b]
-@ FIXME: vqdmulh.s16   d11, d2, d3[0]  @ encoding: [0x92,0xef,0x43,0xbc]
+@ CHECK: vqdmulh.s16   d11, d2, d3[0]  @ encoding: [0x92,0xef,0x43,0xbc]
 
 
        vqrdmulh.s16    d16, d16, d17