config RK_DEBUG_UART
int "Debug UART"
default 1 if ARCH_RK29
- default 2 if ARCH_RK30
+ default 2 if ARCH_RK30 || ARCH_RK2928
help
Select a UART for debugging. -1 disable.
+config RK_USB_UART
+ bool "Support USB UART Bypass Function"
+ depends on ARCH_RK2928 && (RK_DEBUG_UART = 2)
+ default y
+
config RK_CONSOLE_THREAD
bool "Console write by thread"
depends on FIQ_DEBUGGER_CONSOLE
#define RK29_SDMMC_WAIT_DTO_INTERNVAL 4500 //The time interval from the CMD_DONE_INT to DTO_INT
#define RK29_SDMMC_REMOVAL_DELAY 2000 //The time interval from the CD_INT to detect_timer react.
-#define RK29_SDMMC_VERSION "Ver.4.02 The last modify date is 2012-08-12"
+#define RK29_SDMMC_VERSION "Ver.4.03 The last modify date is 2012-08-21"
#if !defined(CONFIG_USE_SDMMC0_FOR_WIFI_DEVELOP_BOARD)
#define RK29_CTRL_SDMMC_ID 0 //mainly used by SDMMC
}
rk29_sdmmc_write(host->regs, SDMMC_CMDARG, cmd->arg); // write to SDMMC_CMDARG register
+#if defined(CONFIG_ARCH_RK29)
rk29_sdmmc_write(host->regs, SDMMC_CMD, cmd_flags | SDMMC_CMD_START); // write to SDMMC_CMD register
-
+#else
+ rk29_sdmmc_write(host->regs, SDMMC_CMD, cmd_flags | SDMMC_CMD_USE_HOLD_REG |SDMMC_CMD_START); // write to SDMMC_CMD register
+#endif
xbwprintk(1,"\n%s..%d..************.start cmd=%d, arg=0x%x ******** [%s]\n", \
__FUNCTION__, __LINE__, cmd->opcode, cmd->arg, host->dma_name);
static int sdmmc_send_cmd_start(struct rk29_sdmmc *host, unsigned int cmd)
{
int tmo = RK29_SDMMC_SEND_START_TIMEOUT*10;//wait 60ms cycle.
-
- rk29_sdmmc_write(host->regs, SDMMC_CMD, SDMMC_CMD_START | cmd);
+
+#if defined(CONFIG_ARCH_RK29)
+ rk29_sdmmc_write(host->regs, SDMMC_CMD, SDMMC_CMD_START | cmd);
+#else
+ rk29_sdmmc_write(host->regs, SDMMC_CMD, SDMMC_CMD_USE_HOLD_REG |SDMMC_CMD_START | cmd);
+#endif
while (--tmo && (rk29_sdmmc_read(host->regs, SDMMC_CMD) & SDMMC_CMD_START))
{
udelay(2);
#if defined(CONFIG_ARCH_RK29)
#define SDMMC_DATA (0x100)
-#elif defined(CONFIG_ARCH_RK30) || defined(CONFIG_ARCH_RK31) || defined(CONFIG_ARCH_RK2928)
+#else
#define SDMMC_VERID (0x06c) //Version ID register
#define SDMMC_UHS_REG (0x074) //UHS-I register
#define SDMMC_RST_n (0x078) //Hardware reset register
/* Interrupt status & mask register defines(base+0x24) */
#if defined(CONFIG_ARCH_RK29)
#define SDMMC_INT_SDIO RK2818_BIT(16) //SDIO interrupt
-#elif defined(CONFIG_ARCH_RK30) || defined(CONFIG_ARCH_RK31) || defined(CONFIG_ARCH_RK2928)
+#else
#define SDMMC_INT_SDIO RK2818_BIT(24) //SDIO interrupt
#define SDMMC_INT_UNBUSY RK2818_BIT(16) //data no busy interrupt
#endif
/* Command register defines(base+0x2C) */
#define SDMMC_CMD_START RK2818_BIT(31) //start command
+#if !defined(CONFIG_ARCH_RK29)
+#define SDMMC_CMD_USE_HOLD_REG RK2818_BIT(29) //Use hold register.
+#define SDMMC_CMD_VOLT_SWITCH RK2818_BIT(28) //Voltage switch bit
+#define SDMMC_CMD_BOOT_MODE RK2818_BIT(27) //set boot mode.
+#define SDMMC_CMD_DISABLE_BOOT RK2818_BIT(26) //disable boot.
+#define SDMMC_CMD_EXPECT_BOOT_ACK RK2818_BIT(25) //Expect Boot Acknowledge.
+#define SDMMC_CMD_ENABLE_BOOT RK2818_BIT(24) //be set only for mandatory boot mode.
+#endif
#define SDMMC_CMD_UPD_CLK RK2818_BIT(21) //update clock register only
#define SDMMC_CMD_INIT RK2818_BIT(15) //send initialization sequence
#define SDMMC_CMD_STOP RK2818_BIT(14) //stop abort command
#define RX_WMARK (0xF) //RX watermark level set to 15
#define TX_WMARK (0x10) //TX watermark level set to 16
-#elif defined(CONFIG_ARCH_RK30) || defined(CONFIG_ARCH_RK31) || defined(CONFIG_ARCH_RK2928)
+#else
#define FIFO_DEPTH (0x100) //FIFO depth = 256 word
#define RX_WMARK_SHIFT (16)
#define TX_WMARK_SHIFT (0)
clk_disable(ahbclk);
#endif
#endif
-//need to be checked @wlf
#ifdef CONFIG_ARCH_RK2928
#ifndef CONFIG_USB20_HOST
otg_phy_con = (unsigned int*)(USBGRF_UOC1_CON5);
dwc_otg_device->phyclk = phyclk;
dwc_otg_device->ahbclk = ahbclk;
#endif
-//need to be checked @wlf
-#if 0//def CONFIG_ARCH_RK2928
+#ifdef CONFIG_ARCH_RK2928
otg_phy_con = (unsigned int*)(USBGRF_UOC0_CON5);
cru_set_soft_reset(SOFT_RST_USBPHY0, true);
cru_set_soft_reset(SOFT_RST_OTGC0, true);
ahbclk = clk_get(NULL, "hclk_otg1");
#endif
#ifdef CONFIG_ARCH_RK2928
- ahbclk = clk_get(NULL, "hclk_otg1"); //need to be checked @wlf
+ ahbclk = clk_get(NULL, "hclk_otg1");
#endif
if (IS_ERR(ahbclk)) {
retval = PTR_ERR(ahbclk);
DWC_DEBUGPL(DBG_PCDV, "disable usb phy\n");
}
#endif
-#if 0//def CONFIG_ARCH_RK2928
+#ifdef CONFIG_ARCH_RK2928
unsigned int * otg_phy_con1 = (unsigned int*)(USBGRF_UOC0_CON5);
- if(exitsuspend && (pcd->phy_suspend == 1)) {
- clk_enable(pcd->otg_dev->ahbclk);
- clk_enable(pcd->otg_dev->phyclk);
- pcd->phy_suspend = 0;
+ if(suspend) {
*otg_phy_con1 = (0x01<<16); // exit suspend.
DWC_DEBUGPL(DBG_PCDV, "enable usb phy\n");
}
- if( !exitsuspend && (pcd->phy_suspend == 0)) {
- pcd->phy_suspend = 1;
- *otg_phy_con1 = 0x55 |(0x7f<<16); // enter suspend.
+ else{
+ *otg_phy_con1 = 0x1D5 |(0x1ff<<16); // enter suspend. enable dm,dp Pull-Down Resistor wlf @2012.8.10
udelay(3);
- clk_disable(pcd->otg_dev->phyclk);
- clk_disable(pcd->otg_dev->ahbclk);
DWC_DEBUGPL(DBG_PCDV, "disable usb phy\n");
}
#endif
}
if(dwc_otg_hcd->host_setenable != dwc_otg_hcd->host_enabled){
#ifdef CONFIG_ARCH_RK30
- DWC_PRINT("%s schedule delaywork 0x%x, 0x%x\n", __func__, dwc_read_reg32(core_if->host_if->hprt0), usbgrf_status& (7<<22));
+ DWC_PRINT("%s schedule delaywork, hprt 0x%08x, grfstatus 0x%08x\n", __func__, dwc_read_reg32(core_if->host_if->hprt0), usbgrf_status& (7<<22));
#else //CONFIG_ARCH_RK2928
- DWC_PRINT("%s schedule delaywork \n", __func__, dwc_read_reg32(core_if->host_if->hprt0), usbgrf_status& (7<<12));
+ DWC_PRINT("%s schedule delaywork, hprt 0x%08x, grfstatus 0x%08x\n", __func__, dwc_read_reg32(core_if->host_if->hprt0), usbgrf_status& (7<<12));
#endif
schedule_delayed_work(&dwc_otg_hcd->host_enable_work, 8);
}
DWC_DEBUGPL(DBG_PCDV, "disable usb phy\n");
}
#endif
-#if 0//def CONFIG_ARCH_RK2928
- unsigned int * otg_phy_con1 = (unsigned int*)(USBGRF_UOC0_CON5);
- if(exitsuspend && (pcd->phy_suspend == 1)) {
- clk_enable(pcd->otg_dev->ahbclk);
- clk_enable(pcd->otg_dev->phyclk);
- pcd->phy_suspend = 0;
+#ifdef CONFIG_ARCH_RK2928
+ unsigned int * otg_phy_con1 = (unsigned int*)(USBGRF_UOC1_CON5);
+ if(suspend) {
*otg_phy_con1 = (0x01<<16); // exit suspend.
DWC_DEBUGPL(DBG_PCDV, "enable usb phy\n");
}
- if( !exitsuspend && (pcd->phy_suspend == 0)) {
- pcd->phy_suspend = 1;
- *otg_phy_con1 = 0x55 |(0x7f<<16); // enter suspend.
+ else{
+ *otg_phy_con1 = 0x1D5 |(0x1ff<<16); // enter suspend. enable dm,dp Pull-Down Resistor wlf @2012.8.10
udelay(3);
- clk_disable(pcd->otg_dev->phyclk);
- clk_disable(pcd->otg_dev->ahbclk);
DWC_DEBUGPL(DBG_PCDV, "disable usb phy\n");
}
#endif
#ifdef CONFIG_ARCH_RK29
#include <mach/cru.h>
#endif
+#include <mach/board.h>
/**
* Static PCD pointer for use in usb_gadget_register_driver and
* usb_gadget_unregister_driver. Initialized in dwc_otg_pcd_init.
}
if( !exitsuspend && (pcd->phy_suspend == 0)) {
pcd->phy_suspend = 1;
- *otg_phy_con1 = 0x55 |(0x7f<<16); // enter suspend.
- // *otg_phy_con1 = 0x1D5 |(0x1ff<<16); // enter suspend. enable dm,dp debug_wlf @2012.8.10
+ *otg_phy_con1 = 0x1D5 |(0x1ff<<16); // enter suspend. enable dm,dp Pull-Down Resistor wlf @2012.8.10
udelay(3);
- clk_disable(pcd->otg_dev->phyclk);
+// otg/host20 use the same phyclk, so can't disable phyclk in case host20 is used. wlf @2012.8.16
+// clk_disable(pcd->otg_dev->phyclk);
clk_disable(pcd->otg_dev->ahbclk);
DWC_DEBUGPL(DBG_PCDV, "disable usb phy\n");
}
/* if usb not connect before ,then start connect */
if( _pcd->vbus_status == 0 ) {
DWC_PRINT("********vbus detect*********************************************\n");
- dwc_otg_msc_lock(_pcd);
_pcd->vbus_status = 1;
if(_pcd->conn_en)
goto connect;
_pcd->conn_status++;
if((dwc_read_reg32((uint32_t*)((uint8_t *)_pcd->otg_dev->base + DWC_OTG_HOST_PORT_REGS_OFFSET))&0xc00) == 0xc00)
_pcd->vbus_status = 2;
+ dwc_otg20phy_suspend(0);
}
}else {
_pcd->vbus_status = 0;
- if(_pcd->conn_status)
- {
+ if(_pcd->conn_status){
_pcd->conn_status = 0;
dwc_otg_msc_unlock(_pcd);
+ rk28_send_wakeup_key();
}
/* every 500 ms open usb phy power and start 1 jiffies timer to get vbus */
- if( _pcd->phy_suspend == 0 )
+ else if( _pcd->phy_suspend == 0 )
/* no vbus detect here , close usb phy */
dwc_otg20phy_suspend( 0 );
}
return;
connect:
+ if(_pcd->conn_status==0)
+ dwc_otg_msc_lock(_pcd);
if( _pcd->phy_suspend == 1 )
dwc_otg20phy_suspend( 1 );
schedule_delayed_work( &_pcd->reconnect , 8 ); /* delay 1 jiffies */