ARM64: rockchip: rk3399: clk: fix i2c4 and i2c8 gate-register
authorElaine Zhang <zhangqing@rock-chips.com>
Thu, 31 Mar 2016 08:34:55 +0000 (16:34 +0800)
committerElaine Zhang <zhangqing@rock-chips.com>
Thu, 31 Mar 2016 08:34:55 +0000 (16:34 +0800)
Fix a typo making the sclk_i2c4 and sclk_i2c8 access a
wrong register bit offset to handle its gate.

Change-Id: I836244b8e14aa34ef44241c8ff24ebd6b63ed23a
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
drivers/clk/rockchip/clk-rk3399.c

index c8f80400e58c5881a2ca6435a92c400eec9bb222..b3f6b8cb6da86b14b7725ed158ea5c3b05aba95f 100644 (file)
@@ -1383,11 +1383,11 @@ static struct rockchip_clk_branch rk3399_clk_pmu_branches[] __initdata = {
 
        COMPOSITE_NOMUX(SCLK_I2C4_PMU, "clk_i2c4_pmu", "ppll", 0,
                        RK3399_PMU_CLKSEL_CON(3), 0, 7, DFLAGS,
-                       RK3399_PMU_CLKGATE_CON(0), 11, GFLAGS),
+                       RK3399_PMU_CLKGATE_CON(0), 10, GFLAGS),
 
        COMPOSITE_NOMUX(SCLK_I2C8_PMU, "clk_i2c8_pmu", "ppll", 0,
                        RK3399_PMU_CLKSEL_CON(2), 8, 7, DFLAGS,
-                       RK3399_PMU_CLKGATE_CON(0), 10, GFLAGS),
+                       RK3399_PMU_CLKGATE_CON(0), 11, GFLAGS),
 
        DIV(0, "clk_32k_suspend_pmu", "xin24m", CLK_IGNORE_UNUSED,
                        RK3399_PMU_CLKSEL_CON(4), 0, 10, DFLAGS),