rk31xx lvds: set iomux for lvds ttl mode

Signed-off-by: hjc <hjc@rock-chips.com>

diff --git a/arch/arm64/boot/dts/rk3368-tb_8846.dts b/arch/arm64/boot/dts/rk3368-tb_8846.dts
index 12862a345b36a25343c2d4f68ba720b8030f51fa..3aa5318ece424a8dc7d9bce5f81943ae90cb9bcd 100755 (executable)
--- a/arch/arm64/boot/dts/rk3368-tb_8846.dts
+++ b/arch/arm64/boot/dts/rk3368-tb_8846.dts
@@ -557,9 +557,12 @@
         display-timings = <&disp_timings>;
 };
 
-&lvds {
+/*&lvds {
        status = "okay";
-};
+       pinctrl-names = "lcdc", "sleep";
+       pinctrl-0 = <&lcdc_lcdc>;
+       pinctrl-1 = <&lcdc_gpio>;
+};*/
 
 &lcdc {
        status = "okay";

diff --git a/arch/arm64/boot/dts/rk3368.dtsi b/arch/arm64/boot/dts/rk3368.dtsi
index e87da004476b2a439f58e4291b35271a9e820ee1..640395ce9f26f4368ebf2272f5b6985e6b5737e3 100644 (file)
--- a/arch/arm64/boot/dts/rk3368.dtsi
+++ b/arch/arm64/boot/dts/rk3368.dtsi
@@ -678,9 +678,10 @@
                 rockchip,iommu-enabled = <0>;
                 reg = <0x0 0xff930000 0x0 0x10000>;
                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
-                pinctrl-names = "default", "gpio";
-                pinctrl-0 = <&lcdc_lcdc>;
-                pinctrl-1 = <&lcdc_gpio>;
+               /*pinctrl-names = "default", "gpio";
+                *pinctrl-0 = <&lcdc_lcdc>;
+                *pinctrl-1 = <&lcdc_gpio>;
+                */
                 status = "disabled";
                 clocks = <&clk_gates16 5>, <&dclk_vop0>, <&clk_gates16 6>, <&clk_npll>;
                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc", "sclk_pll";
@@ -1576,14 +1577,44 @@
 
                lcdc {
                        lcdc_lcdc: lcdc-lcdc {
-                               rockchip,pins = <0 GPIO_D7 RK_FUNC_1 &pcfg_pull_none>,//DCLK
+                               rockchip,pins =
+                                               <0 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D10
+                                               <0 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D11
+                                               <0 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D12
+                                               <0 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D13
+                                               <0 GPIO_C2 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D14
+                                               <0 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D15
+                                               <0 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D16
+                                               <0 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D17
+                                               <0 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D18
+                                               <0 GPIO_C7 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D19
+                                               <0 GPIO_D0 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D20
+                                               <0 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D21
+                                               <0 GPIO_D2 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D22
+                                               <0 GPIO_D3 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D23
+                                               <0 GPIO_D7 RK_FUNC_1 &pcfg_pull_none>,//DCLK
                                                <0 GPIO_D6 RK_FUNC_1 &pcfg_pull_none>,//DEN
                                                <0 GPIO_D4 RK_FUNC_1 &pcfg_pull_none>,//HSYNC
                                                <0 GPIO_D5 RK_FUNC_1 &pcfg_pull_none>;//VSYN
                        };
 
                        lcdc_gpio: lcdc-gpio {
-                               rockchip,pins = <0 GPIO_D7 RK_FUNC_GPIO &pcfg_pull_none>,//DCLK
+                               rockchip,pins =
+                                               <0 GPIO_B6 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D10
+                                               <0 GPIO_B7 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D11
+                                               <0 GPIO_C0 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D12
+                                               <0 GPIO_C1 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D13
+                                               <0 GPIO_C2 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D14
+                                               <0 GPIO_C3 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D15
+                                               <0 GPIO_C4 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D16
+                                               <0 GPIO_C5 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D17
+                                               <0 GPIO_C6 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D18
+                                               <0 GPIO_C7 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D19
+                                               <0 GPIO_D0 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D20
+                                               <0 GPIO_D1 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D21
+                                               <0 GPIO_D2 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D22
+                                               <0 GPIO_D3 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D23
+                                               <0 GPIO_D7 RK_FUNC_GPIO &pcfg_pull_none>,//DCLK
                                                <0 GPIO_D6 RK_FUNC_GPIO &pcfg_pull_none>,//DEN
                                                <0 GPIO_D4 RK_FUNC_GPIO &pcfg_pull_none>,//HSYNC
                                                <0 GPIO_D5 RK_FUNC_GPIO &pcfg_pull_none>;//VSYN

diff --git a/drivers/video/rockchip/transmitter/rk31xx_lvds.c b/drivers/video/rockchip/transmitter/rk31xx_lvds.c
index ff8e39b5953d3755553ffee60e6ccae350f92e57..f0bceca1abf672862988dd93d9da74160a23ac04 100644 (file)
--- a/drivers/video/rockchip/transmitter/rk31xx_lvds.c
+++ b/drivers/video/rockchip/transmitter/rk31xx_lvds.c
@@ -187,8 +187,7 @@ static void rk31xx_output_lvds(struct rk_lvds_device *lvds,
                       v_RK3368_MIPIDPI_FORCEX_EN(1);
                /*rk3368  RK3368_GRF_SOC_CON7 = 0X0041C*/
                /*grf_writel(val, 0x0041C);*/
-               regmap_write(lvds->grf_lvds_base, GRF_SOC_CON7_LVDS, val);
-               dsb(sy);
+               lvds_grf_writel(lvds, GRF_SOC_CON7_LVDS, val);
        } else {
                /* enable lvds mode */
                val |= v_LVDSMODE_EN(1) | v_MIPIPHY_TTL_EN(0);
@@ -242,28 +241,46 @@ static void rk31xx_output_lvttl(struct rk_lvds_device *lvds,
 {
         u32 val = 0;
 
-        /* iomux to lcdc */
+       if (lvds->data->soc_type == LVDS_SOC_RK3368) {
+               /* iomux to lcdc */
+#ifdef CONFIG_PINCTRL
+               if (lvds->pins && !IS_ERR(lvds->pins->default_state))
+                       pinctrl_select_state(lvds->pins->p,
+                                            lvds->pins->default_state);
+#endif
+               /* enable lvds mode */
+               val |= v_RK3368_LVDSMODE_EN(0) | v_RK3368_MIPIPHY_TTL_EN(1);
+               lvds_grf_writel(lvds, GRF_SOC_CON7_LVDS, val);
+
+               /*val = v_MIPITTL_CLK_EN(1) | v_MIPITTL_LANE0_EN(1) |
+               v_MIPITTL_LANE1_EN(1) | v_MIPITTL_LANE2_EN(1) |
+               v_MIPITTL_LANE3_EN(1);
+               grf_writel(val, RK312X_GRF_SOC_CON1);*/
+       } else {
+               /* iomux to lcdc */
 #if defined(CONFIG_RK_FPGA)
-        grf_writel(0xffff5555, RK312X_GRF_GPIO2B_IOMUX);
-        grf_writel(0x00ff0055, RK312X_GRF_GPIO2C_IOMUX);
-        grf_writel(0x77771111, 0x00e8); /* RK312X_GRF_GPIO2C_IOMUX2 */
-        grf_writel(0x700c1004, RK312X_GRF_GPIO2D_IOMUX);
+               grf_writel(0xffff5555, RK312X_GRF_GPIO2B_IOMUX);
+               grf_writel(0x00ff0055, RK312X_GRF_GPIO2C_IOMUX);
+               grf_writel(0x77771111, 0x00e8); /* RK312X_GRF_GPIO2C_IOMUX2 */
+               grf_writel(0x700c1004, RK312X_GRF_GPIO2D_IOMUX);
 #else
 #ifdef CONFIG_PINCTRL
-        if (lvds->pins && !IS_ERR(lvds->pins->default_state))
-                pinctrl_select_state(lvds->pins->p, lvds->pins->default_state);
+               if (lvds->pins && !IS_ERR(lvds->pins->default_state))
+                       pinctrl_select_state(lvds->pins->p,
+                                            lvds->pins->default_state);
 #endif
 #endif
+               /* enable lvds mode */
+               val |= v_LVDSMODE_EN(0) | v_MIPIPHY_TTL_EN(1);
+               /* config data source */
+               val |= v_LVDS_DATA_SEL(LVDS_DATA_FROM_LCDC);
+               grf_writel(0xffff0380, RK312X_GRF_LVDS_CON0);
 
-       val |= v_LVDSMODE_EN(0) | v_MIPIPHY_TTL_EN(1);  /* enable lvds mode */
-       val |= v_LVDS_DATA_SEL(LVDS_DATA_FROM_LCDC);    /* config data source */
-       grf_writel(0xffff0380, RK312X_GRF_LVDS_CON0);
-
-        val = v_MIPITTL_CLK_EN(1) | v_MIPITTL_LANE0_EN(1) |
-                v_MIPITTL_LANE1_EN(1) | v_MIPITTL_LANE2_EN(1) |
-                v_MIPITTL_LANE3_EN(1);
-        grf_writel(val, RK312X_GRF_SOC_CON1);
-
+               val = v_MIPITTL_CLK_EN(1) | v_MIPITTL_LANE0_EN(1) |
+                       v_MIPITTL_LANE1_EN(1) | v_MIPITTL_LANE2_EN(1) |
+                       v_MIPITTL_LANE3_EN(1);
+               grf_writel(val, RK312X_GRF_SOC_CON1);
+       }
         /* enable lane */
         lvds_writel(lvds, MIPIPHY_REG0, 0x7f);
         val = v_LANE0_EN(1) | v_LANE1_EN(1) | v_LANE2_EN(1) | v_LANE3_EN(1) |

diff --git a/drivers/video/rockchip/transmitter/rk31xx_lvds.h b/drivers/video/rockchip/transmitter/rk31xx_lvds.h
old mode 100755 (executable)
new mode 100644 (file)
index 2ce76de..1ba2696
--- a/drivers/video/rockchip/transmitter/rk31xx_lvds.h
+++ b/drivers/video/rockchip/transmitter/rk31xx_lvds.h
@@ -155,6 +155,15 @@ static inline u32 lvds_readl(struct rk_lvds_device *lvds, u32 offset)
        return readl_relaxed(lvds->regbase + offset);
 }
 
+static inline int lvds_grf_writel(struct rk_lvds_device *lvds,
+                                 u32 offset, u32 val)
+{
+       regmap_write(lvds->grf_lvds_base, offset, val);
+       dsb(sy);
+
+       return 0;
+}
+
 static inline u32 lvds_phy_lockon(struct rk_lvds_device *lvds)
 {
        u32 val = 0;