ARM64: dts: rk3366: add config for display

Change-Id: I2112b26b762c56da1c621332743e376255669646
Signed-off-by: Huang Jiachai <hjc@rock-chips.com>

diff --git a/arch/arm64/boot/dts/rockchip/rk3366-fpga.dts b/arch/arm64/boot/dts/rockchip/rk3366-fpga.dts
index 278d607e9c5ef8fefd15697c8419a7e5953c08f5..4f7b0db9cfbdc34d28796482af3f3603dd069a36 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3366-fpga.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3366-fpga.dts
@@ -43,6 +43,7 @@
 /dts-v1/;
 
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/display/rk_fb.h>
 
 / {
        model = "rockchip,rk3366-fpga";
@@ -134,6 +135,97 @@
                reg-io-width = <4>;
        };
 
+       ion {
+               compatible = "rockchip,ion";
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               cma-heap {
+                       reg = <0x00000000 0x01000000>;
+               };
+
+               system-heap {
+               };
+       };
+
+       grf: syscon@ff770000 {
+               compatible = "rockchip,rk3368-grf", "syscon";
+               reg = <0x0 0xff770000 0x0 0x1000>;
+       };
+
+       fb: fb {
+               compatible = "rockchip,rk-fb";
+               rockchip,disp-mode = <NO_DUAL>;
+               status = "disabled";
+       };
+
+       rk_screen: screen {
+               compatible = "rockchip,screen";
+               status = "disabled";
+               #include <dt-bindings/display/screen-timing/lcd-fpga-800x480-rgb.dtsi>
+       };
+
+       lvds: lvds@ff968000 {
+               compatible = "rockchip,rk3366-lvds";
+               rockchip,grf = <&grf>;
+               reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600a0 0x0 0x20>;
+               reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
+               /* clocks = <&cru PCLK_DPHYTX>, <&cru PCLK_MIPI_DSI0>;
+                * clock-names = "pclk_lvds", "pclk_lvds_ctl";
+                */
+               status = "disabled";
+       };
+
+       vop_lite: vop@ff8f0000 {
+               compatible = "rockchip,rk3366-lcdc-lite";
+               rockchip,grf = <&grf>;
+               rockchip,prop = <EXTEND>;
+               rockchip,pwr18 = <0>;
+               rockchip,iommu-enabled = <1>;
+               reg = <0x0 0xff8f0000 0x0 0x1000>;
+               interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+               /* clocks = <&cru ACLK_VOP_LITE>, <&cru DCLK_VOP_LITE>, <&cru HCLK_VOP_LITE>;
+                * clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
+                * resets = <&cru SRST_VOP1_AXI>, <&cru SRST_VOP1_DCLK>, <&cru SRST_VOP1_AHB>;
+                * reset-names = "axi", "ahb", "dclk";
+                */
+               status = "disabled";
+       };
+
+       vopl_mmu: vopl-mmu {
+               dbgname = "vop";
+               compatible = "rockchip,vopl_mmu";
+               reg = <0x0 0xff8f0f00 0x0 0x100>;
+               interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-names = "vopl_mmu";
+               status = "disabled";
+       };
+
+       vop_big: vop@ff930000 {
+               compatible = "rockchip,rk3366-lcdc-big";
+               rockchip,grf = <&grf>;
+               rockchip,prop = <PRMRY>;
+               rockchip,pwr18 = <0>;
+               rockchip,iommu-enabled = <1>;
+               reg = <0x0 0xff930000 0x0 0x23f0>;
+               interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+               /* clocks = <&cru ACLK_VOP_FULL>, <&cru DCLK_VOP_FULL>, <&cru HCLK_VOP_FULL>;
+                * clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
+                * resets = <&cru SRST_VOP0_AXI>, <&cru SRST_VOP0_DCLK>, <&cru SRST_VOP0_AHB>;
+                * reset-names = "axi", "ahb", "dclk";
+                */
+               status = "disabled";
+       };
+
+       vopb_mmu: vopb-mmu {
+               dbgname = "vop";
+               compatible = "rockchip,vopb_mmu";
+               reg = <0x0 0xff932400 0x0 0x100>;
+               interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-names = "vop_mmu";
+               status = "disabled";
+       };
+
        gic: interrupt-controller@ffb70000 {
                compatible = "arm,gic-400";
                #interrupt-cells = <3>;

diff --git a/arch/arm64/boot/dts/rockchip/rk3366-tb.dts b/arch/arm64/boot/dts/rockchip/rk3366-tb.dts
index c70263c2a455b75154043e4ef7d1cc6c7c5a6f24..2ca32e47a5a0867928f54c300e57cf38d76751af 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3366-tb.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3366-tb.dts
@@ -214,3 +214,66 @@
        status = "okay";
 };
 
+&fb {
+       status = "okay";
+       rockchip,disp-mode = <DUAL>;
+       rockchip,uboot-logo-on = <0>;
+};
+
+&rk_screen {
+       status = "okay";
+       #include <dt-bindings/display/screen-timing/lcd-b101ew05.dtsi>
+};
+
+&lvds {
+       pinctrl-names = "lcdc", "sleep";
+       pinctrl-0 = <&lcdc_lcdc>;
+       pinctrl-1 = <&lcdc_gpio>;
+       status = "disabled";
+};
+
+&vop_lite {
+       status = "okay";
+       rockchip,prop = <EXTEND>;
+       rockchip,mirror = <NO_MIRROR>;
+       rockchip,cabc_mode = <0>;
+       rockchip,fb-win-map = <FB_DEFAULT_ORDER>;
+};
+
+&vopl_mmu {
+       status = "okay";
+};
+
+&vop_big {
+       status = "okay";
+       rockchip,prop = <PRMRY>;
+       backlight = <&backlight>;
+       rockchip,mirror = <NO_MIRROR>;
+       rockchip,cabc_mode = <0>;
+       rockchip,fb-win-map = <FB_DEFAULT_ORDER>;
+       power_ctr: power_ctr {
+               rockchip,debug = <0>;
+               lcd_en: lcd-en {
+                       rockchip,power_type = <GPIO>;
+                       gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; /* GPIO_B4 = 12 */
+                       rockchip,delay = <10>;
+               };
+
+               lcd_cs: lcd-cs {
+                       rockchip,power_type = <GPIO>;
+                       gpios = <&gpio0 24 GPIO_ACTIVE_HIGH>; /* GPIO_D0 = 24 */
+                       rockchip,delay = <10>;
+               };
+
+               /* lcd_rst: lcd-rst {
+                *      rockchip,power_type = <GPIO>;
+                *      gpios = <&gpio3 GPIO_D6 GPIO_ACTIVE_HIGH>;
+                *      rockchip,delay = <5>;
+                * };
+                */
+       };
+};
+
+&vopb_mmu {
+       status = "okay";
+};
\ No newline at end of file

diff --git a/arch/arm64/boot/dts/rockchip/rk3366.dtsi b/arch/arm64/boot/dts/rockchip/rk3366.dtsi
index 1916e3e68d5e4f1b8533203acc047ea27a50586c..627bc2e6e38a2104f3b79e11cb791696125566d3 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3366.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3366.dtsi
@@ -45,6 +45,7 @@
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/display/rk_fb.h>
 
 / {
        compatible = "rockchip,rk3366";
@@ -427,6 +428,64 @@
                reg = <0x0 0xff770000 0x0 0x1000>;
        };
 
+       fb: fb {
+               compatible = "rockchip,rk-fb";
+               rockchip,disp-mode = <DUAL>;
+               status = "disabled";
+       };
+
+       rk_screen: screen {
+               compatible = "rockchip,screen";
+               status = "disabled";
+       };
+
+       vop_lite: vop@ff8f0000 {
+               compatible = "rockchip,rk3366-lcdc-lite";
+               rockchip,grf = <&grf>;
+               rockchip,pwr18 = <0>;
+               rockchip,iommu-enabled = <1>;
+               reg = <0x0 0xff8f0000 0x0 0x1000>;
+               interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cru ACLK_VOP_LITE>, <&cru DCLK_VOP_LITE>, <&cru HCLK_VOP_LITE>;
+               clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
+               resets = <&cru SRST_VOP1_AXI>, <&cru SRST_VOP1_DCLK>, <&cru SRST_VOP1_AHB>;
+               reset-names = "axi", "ahb", "dclk";
+               status = "disabled";
+       };
+
+       vopl_mmu: vopl-mmu {
+               dbgname = "vop";
+               compatible = "rockchip,vopl_mmu";
+               reg = <0x0 0xff8f0f00 0x0 0x100>;
+               interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-names = "vopl_mmu";
+               status = "disabled";
+       };
+
+       vop_big: vop@ff930000 {
+               compatible = "rockchip,rk3366-lcdc-big";
+               rockchip,grf = <&grf>;
+               rockchip,prop = <PRMRY>;
+               rockchip,pwr18 = <0>;
+               rockchip,iommu-enabled = <1>;
+               reg = <0x0 0xff930000 0x0 0x23f0>;
+               interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cru ACLK_VOP_FULL>, <&cru DCLK_VOP_FULL>, <&cru HCLK_VOP_FULL>;
+               clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
+               resets = <&cru SRST_VOP0_AXI>, <&cru SRST_VOP0_DCLK>, <&cru SRST_VOP0_AHB>;
+               reset-names = "axi", "ahb", "dclk";
+               status = "disabled";
+       };
+
+       vopb_mmu: vopb-mmu {
+               dbgname = "vop";
+               compatible = "rockchip,vopb_mmu";
+               reg = <0x0 0xff932400 0x0 0x100>;
+               interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-names = "vop_mmu";
+               status = "disabled";
+       };
+
        dsihost0: mipi@ff960000 {
                compatible = "rockchip,rk3368-dsi";
                rockchip,prop = <0>;
@@ -438,6 +497,16 @@
                status = "disabled";
        };
 
+       lvds: lvds@ff968000 {
+               compatible = "rockchip,rk3366-lvds";
+               rockchip,grf = <&grf>;
+               reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600a0 0x0 0x20>;
+               reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
+               clocks = <&cru PCLK_DPHYTX>, <&cru PCLK_MIPI_DSI0>;
+               clock-names = "pclk_lvds", "pclk_lvds_ctl";
+               status = "disabled";
+       };
+
        pinctrl: pinctrl {
                compatible = "rockchip,rk3366-pinctrl";
                rockchip,grf = <&grf>;
@@ -861,5 +930,51 @@
                                        <5 18 RK_FUNC_2 &pcfg_pull_none>;
                        };
                };
+
+               lcdc {
+                       lcdc_lcdc: lcdc-lcdc {
+                               rockchip,pins =
+                                       <0 24 RK_FUNC_2 &pcfg_pull_none>, /* HSYNC */
+                                       <0 25 RK_FUNC_2 &pcfg_pull_none>, /* VSYNC */
+                                       <0 26 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D10 */
+                                       <0 27 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D11 */
+                                       <0 28 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D12 */
+                                       <0 29 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D13 */
+                                       <0 30 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D14 */
+                                       <0 31 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D15 */
+                                       <1 0  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D16 */
+                                       <1 1  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D17 */
+                                       <1 2  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D18 */
+                                       <1 3  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D19 */
+                                       <1 4  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D20 */
+                                       <1 5  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D21 */
+                                       <1 6  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D22 */
+                                       <1 7  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D23 */
+                                       <1 8  RK_FUNC_1 &pcfg_pull_none>, /* DEN */
+                                       <1 9  RK_FUNC_1 &pcfg_pull_none>; /* DCLK */
+                       };
+
+                       lcdc_gpio: lcdc-gpio {
+                               rockchip,pins =
+                                       <0 24 RK_FUNC_GPIO &pcfg_pull_none>, /* HSYNC */
+                                       <0 25 RK_FUNC_GPIO &pcfg_pull_none>, /* VSYNC */
+                                       <0 26 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D10 */
+                                       <0 27 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D11 */
+                                       <0 28 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D12 */
+                                       <0 29 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D13 */
+                                       <0 30 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D14 */
+                                       <0 31 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D15 */
+                                       <1 0  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D16 */
+                                       <1 1  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D17 */
+                                       <1 2  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D18 */
+                                       <1 3  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D19 */
+                                       <1 4  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D20 */
+                                       <1 5  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D21 */
+                                       <1 6  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D22 */
+                                       <1 7  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D23 */
+                                       <1 8  RK_FUNC_GPIO &pcfg_pull_none>, /* DEN */
+                                       <1 9  RK_FUNC_GPIO &pcfg_pull_none>; /* DCLK */
+                       };
+               };
        };
 };