ARM: mediatek: Add basic support for mt8135
authorJoe.C <yingjoe.chen@mediatek.com>
Tue, 11 Nov 2014 07:53:43 +0000 (15:53 +0800)
committerMatthias Brugger <matthias.bgg@gmail.com>
Wed, 12 Nov 2014 16:31:52 +0000 (17:31 +0100)
This adds a basic dtsi for MT8135 based SoC.

Signed-off-by: Joe.C <yingjoe.chen@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
arch/arm/boot/dts/mt8135.dtsi [new file with mode: 0644]
arch/arm/mach-mediatek/mediatek.c

diff --git a/arch/arm/boot/dts/mt8135.dtsi b/arch/arm/boot/dts/mt8135.dtsi
new file mode 100644 (file)
index 0000000..7d56a98
--- /dev/null
@@ -0,0 +1,116 @@
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ * Author: Joe.C <yingjoe.chen@mediatek.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "skeleton64.dtsi"
+
+/ {
+       compatible = "mediatek,mt8135";
+       interrupt-parent = <&gic>;
+
+       cpu-map {
+               cluster0 {
+                       core0 {
+                               cpu = <&cpu0>;
+                       };
+                       core1 {
+                               cpu = <&cpu1>;
+                       };
+               };
+
+               cluster1 {
+                       core0 {
+                               cpu = <&cpu2>;
+                       };
+                       core1 {
+                               cpu = <&cpu3>;
+                       };
+               };
+       };
+
+       cpus {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               cpu0: cpu@0 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a7";
+                       reg = <0x000>;
+               };
+
+               cpu1: cpu@1 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a7";
+                       reg = <0x001>;
+               };
+
+               cpu2: cpu@100 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a15";
+                       reg = <0x100>;
+               };
+
+               cpu3: cpu@101 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a15";
+                       reg = <0x101>;
+               };
+       };
+
+       clocks {
+               #address-cells = <2>;
+               #size-cells = <2>;
+               compatible = "simple-bus";
+               ranges;
+
+               system_clk: dummy13m {
+                       compatible = "fixed-clock";
+                       clock-frequency = <13000000>;
+                       #clock-cells = <0>;
+               };
+
+               rtc_clk: dummy32k {
+                       compatible = "fixed-clock";
+                       clock-frequency = <32000>;
+                       #clock-cells = <0>;
+               };
+       };
+
+       soc {
+               #address-cells = <2>;
+               #size-cells = <2>;
+               compatible = "simple-bus";
+               ranges;
+
+               timer: timer@10008000 {
+                       compatible = "mediatek,mt8135-timer",
+                                       "mediatek,mt6577-timer";
+                       reg = <0 0x10008000 0 0x80>;
+                       interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&system_clk>, <&rtc_clk>;
+                       clock-names = "system-clk", "rtc-clk";
+               };
+
+               gic: interrupt-controller@10211000 {
+                       compatible = "arm,cortex-a15-gic";
+                       interrupt-controller;
+                       #interrupt-cells = <3>;
+                       reg = <0 0x10211000 0 0x1000>,
+                             <0 0x10212000 0 0x1000>,
+                             <0 0x10214000 0 0x2000>,
+                             <0 0x10216000 0 0x2000>;
+               };
+       };
+};
index 7f478cea0655458919ae118f76883b4c3e94a9c4..48051a205414160c11e154cc65be98724077a4ff 100644 (file)
@@ -20,6 +20,7 @@
 static const char * const mediatek_board_dt_compat[] = {
        "mediatek,mt6589",
        "mediatek,mt8127",
+       "mediatek,mt8135",
        NULL,
 };