static struct workqueue_struct *dvfs_wq;\r
#define PD_ON 1\r
#define PD_OFF 0\r
-#define DVFS_STR(on) ((on) ? "enable" : "disable")\r
+#define DVFS_STR_DISABLE(on) ((on)?"enable":"disable")\r
\r
#define get_volt_up_delay(new_volt, old_volt) \\r
((new_volt) > (old_volt) ? (((new_volt) - (old_volt)) >> 9) : 0)\r
\r
\r
/**************************************vd regulator functions***************************************/\r
-static void dvfs_volt_up_delay(struct vd_node *vd, int new_volt, int old_volt)\r
+static void dvfs_volt_up_delay(struct vd_node *vd,int new_volt, int old_volt)\r
{\r
int u_time;\r
- if(new_volt <= old_volt)\r
+ if(new_volt<=old_volt)\r
return;\r
- if(vd->volt_time_flag > 0)\r
- u_time = regulator_set_voltage_time(vd->regulator, old_volt, new_volt);\r
+ if(vd->volt_time_flag>0) \r
+ u_time=regulator_set_voltage_time(vd->regulator,old_volt,new_volt);\r
else\r
- u_time = -1;\r
- if(u_time < 0) { // regulator is not suported time,useing default time\r
+ u_time=-1; \r
+ if(u_time<0)// regulator is not suported time,useing default time\r
+ {\r
DVFS_DBG("%s:vd %s is not suported getting delay time,so we use default\n",\r
- __FUNCTION__, vd->name);\r
- u_time = ((new_volt) - (old_volt)) >> 9;\r
+ __FUNCTION__,vd->name);\r
+ u_time=((new_volt) - (old_volt)) >> 9;\r
}\r
- DVFS_DBG("%s:vd %s volt %d to %d delay %d us\n", __FUNCTION__, vd->name,\r
- old_volt, new_volt, u_time);\r
+ DVFS_DBG("%s:vd %s volt %d to %d delay %d us\n",__FUNCTION__,vd->name,\r
+ old_volt,new_volt,u_time);\r
if (u_time >= 1000) {\r
mdelay(u_time / 1000);\r
udelay(u_time % 1000);\r
- DVFS_ERR("regulator set vol delay is larger 1ms,old is %d,new is %d\n", old_volt, new_volt);\r
+ DVFS_ERR("regulator set vol delay is larger 1ms,old is %d,new is %d\n",old_volt,new_volt);\r
} else if (u_time) {\r
udelay(u_time);\r
- }\r
+ } \r
}\r
int dvfs_regulator_set_voltage_readback(struct regulator *regulator, int min_uV, int max_uV)\r
{\r
void clk_enable_dvfs_regulator_check(struct vd_node *vd)\r
{\r
vd->cur_volt = dvfs_regulator_get_voltage(vd->regulator);\r
- if(vd->cur_volt <= 0) {\r
+ if(vd->cur_volt<=0)\r
+ {\r
vd->volt_set_flag = DVFS_SET_VOLT_FAILURE;\r
}\r
vd->volt_set_flag = DVFS_SET_VOLT_SUCCESS;\r
\r
static void dvfs_get_vd_regulator_volt_list(struct vd_node *vd)\r
{\r
- unsigned i, selector = dvfs_regulator_count_voltages(vd->regulator);\r
- int sel_volt = 0;\r
-\r
- if(selector > VD_VOL_LIST_CNT)\r
- selector = VD_VOL_LIST_CNT;\r
-\r
+ unsigned i,selector=dvfs_regulator_count_voltages(vd->regulator);\r
+ int sel_volt=0;\r
+ \r
+ if(selector>VD_VOL_LIST_CNT)\r
+ selector=VD_VOL_LIST_CNT;\r
+ \r
mutex_lock(&mutex);\r
- for (i = 0; i < selector; i++) {\r
- sel_volt = dvfs_regulator_list_voltage(vd->regulator, i);\r
- if(sel_volt <= 0) {\r
- DVFS_WARNING("%s : selector=%u,but volt <=0\n", vd->name, i);\r
+ for (i = 0; i<selector; i++) {\r
+ sel_volt=dvfs_regulator_list_voltage(vd->regulator,i);\r
+ if(sel_volt<=0)\r
+ { \r
+ DVFS_WARNING("%s : selector=%u,but volt <=0\n",vd->name,i);\r
break;\r
}\r
- vd->volt_list[i] = sel_volt;\r
- DVFS_DBG("%s:selector=%u,volt %d\n", vd->name, i, sel_volt);\r
+ vd->volt_list[i]=sel_volt; \r
+ DVFS_DBG("%s:selector=%u,volt %d\n",vd->name,i,sel_volt);\r
}\r
- vd->n_voltages = selector;\r
+ vd->n_voltages=selector;\r
mutex_unlock(&mutex);\r
}\r
\r
{\r
int sel_volt;\r
unsigned i;\r
-\r
- for (i = 0; i < vd->n_voltages; i++) {\r
- sel_volt = vd->volt_list[i];\r
- if(sel_volt <= 0) {\r
- DVFS_WARNING("%s:list_volt : selector=%u,but volt <=0\n", __FUNCTION__, i);\r
+ \r
+ for (i = 0; i<vd->n_voltages; i++) {\r
+ sel_volt=vd->volt_list[i];\r
+ if(sel_volt<=0)\r
+ { \r
+ DVFS_WARNING("%s:list_volt : selector=%u,but volt <=0\n",__FUNCTION__,i);\r
return -1;\r
}\r
- if(sel_volt >= volt)\r
- return sel_volt;\r
+ if(sel_volt>=volt)\r
+ return sel_volt; \r
}\r
return -1;\r
}\r
{\r
int sel_volt;\r
unsigned i;\r
-\r
- for (i = 0; i < vd->n_voltages; i++) {\r
- sel_volt = vd->volt_list[i];\r
- if(sel_volt <= 0) {\r
- DVFS_WARNING("%s:list_volt : selector=%u,but volt <=0\n", __FUNCTION__, i);\r
+ \r
+ for (i = 0; i<vd->n_voltages; i++) {\r
+ sel_volt=vd->volt_list[i];\r
+ if(sel_volt<=0)\r
+ { \r
+ DVFS_WARNING("%s:list_volt : selector=%u,but volt <=0\n",__FUNCTION__,i);\r
return -1;\r
}\r
- if(sel_volt > volt) {\r
- if(i > 0)\r
+ if(sel_volt>volt)\r
+ {\r
+ if(i>0)\r
return vd->volt_list[i-1];\r
else\r
return -1;\r
- }\r
+ } \r
}\r
return -1;\r
}\r
\r
// >=volt\r
-int vd_regulator_round_volt(struct vd_node *vd, int volt, int flags)\r
+int vd_regulator_round_volt(struct vd_node *vd, int volt,int flags)\r
{\r
if(!vd->n_voltages)\r
return -1;\r
- if(flags == VD_LIST_RELATION_L)\r
- return vd_regulator_round_volt_min(vd, volt);\r
+ if(flags==VD_LIST_RELATION_L)\r
+ return vd_regulator_round_volt_min(vd,volt);\r
else\r
- return vd_regulator_round_volt_max(vd, volt);\r
+ return vd_regulator_round_volt_max(vd,volt); \r
}\r
EXPORT_SYMBOL(vd_regulator_round_volt);\r
\r
\r
static void dvfs_table_round_volt(struct clk_node *dvfs_clk)\r
{\r
- int i, test_volt;\r
+ int i,test_volt;\r
\r
- if(!dvfs_clk->dvfs_table || !dvfs_clk->vd || IS_ERR_OR_NULL(dvfs_clk->vd->regulator))\r
+ if(!dvfs_clk->dvfs_table||!dvfs_clk->vd||IS_ERR_OR_NULL(dvfs_clk->vd->regulator))\r
return;\r
mutex_lock(&mutex);\r
for (i = 0; (dvfs_clk->dvfs_table[i].frequency != CPUFREQ_TABLE_END); i++) {\r
\r
- test_volt = vd_regulator_round_volt(dvfs_clk->vd, dvfs_clk->dvfs_table[i].index, VD_LIST_RELATION_H);\r
- if(test_volt <= 0) {\r
- DVFS_WARNING("clk %s:round_volt : is %d,but list <=0\n", dvfs_clk->name, dvfs_clk->dvfs_table[i].index);\r
+ test_volt=vd_regulator_round_volt(dvfs_clk->vd,dvfs_clk->dvfs_table[i].index,VD_LIST_RELATION_H);\r
+ if(test_volt<=0)\r
+ { \r
+ DVFS_WARNING("clk %s:round_volt : is %d,but list <=0\n",dvfs_clk->name,dvfs_clk->dvfs_table[i].index);\r
break;\r
}\r
- DVFS_DBG("clk %s:round_volt %d to %d\n", dvfs_clk->name, dvfs_clk->dvfs_table[i].index, test_volt);\r
- dvfs_clk->dvfs_table[i].index = test_volt;\r
+ DVFS_DBG("clk %s:round_volt %d to %d\n",dvfs_clk->name,dvfs_clk->dvfs_table[i].index,test_volt);\r
+ dvfs_clk->dvfs_table[i].index=test_volt; \r
}\r
mutex_unlock(&mutex);\r
}\r
void dvfs_vd_get_regulator_volt_time_info(struct vd_node *vd)\r
{\r
- if(vd->volt_time_flag <= 0) { // check regulator support get uping vol timer\r
- vd->volt_time_flag = dvfs_regulator_set_voltage_time(vd->regulator, vd->cur_volt, vd->cur_volt + 200 * 1000);\r
- if(vd->volt_time_flag < 0) {\r
- DVFS_DBG("%s,vd %s volt_time is no support\n", __FUNCTION__, vd->name);\r
- } else {\r
- DVFS_DBG("%s,vd %s volt_time is support,up 200mv need delay %d us\n", __FUNCTION__, vd->name, vd->volt_time_flag);\r
-\r
+ if(vd->volt_time_flag<=0)// check regulator support get uping vol timer\r
+ {\r
+ vd->volt_time_flag=dvfs_regulator_set_voltage_time(vd->regulator,vd->cur_volt,vd->cur_volt+200*1000);\r
+ if(vd->volt_time_flag<0)\r
+ {\r
+ DVFS_DBG("%s,vd %s volt_time is no support\n",__FUNCTION__,vd->name);\r
}\r
+ else\r
+ {\r
+ DVFS_DBG("%s,vd %s volt_time is support,up 200mv need delay %d us\n",__FUNCTION__,vd->name,vd->volt_time_flag);\r
+\r
+ } \r
}\r
}\r
\r
void dvfs_vd_get_regulator_mode_info(struct vd_node *vd)\r
{\r
//REGULATOR_MODE_FAST\r
- if(vd->mode_flag <= 0) { // check regulator support get uping vol timer\r
- vd->mode_flag = dvfs_regulator_get_mode(vd->regulator);\r
- if(vd->mode_flag == REGULATOR_MODE_FAST || vd->mode_flag == REGULATOR_MODE_NORMAL\r
- || vd->mode_flag == REGULATOR_MODE_IDLE || vd->mode_flag == REGULATOR_MODE_STANDBY) {\r
- if(dvfs_regulator_set_mode(vd->regulator, vd->mode_flag) < 0) {\r
- vd->mode_flag = 0; // check again\r
+ if(vd->mode_flag<=0)// check regulator support get uping vol timer\r
+ {\r
+ vd->mode_flag=dvfs_regulator_get_mode(vd->regulator);\r
+ if(vd->mode_flag==REGULATOR_MODE_FAST||vd->mode_flag==REGULATOR_MODE_NORMAL\r
+ ||vd->mode_flag==REGULATOR_MODE_IDLE||vd->mode_flag==REGULATOR_MODE_STANDBY)\r
+ {\r
+ if(dvfs_regulator_set_mode(vd->regulator,vd->mode_flag)<0)\r
+ {\r
+ vd->mode_flag=0;// check again\r
}\r
-\r
+ \r
}\r
- if(vd->mode_flag > 0) {\r
- DVFS_DBG("%s,vd %s mode(now is %d) support\n", __FUNCTION__, vd->name, vd->mode_flag);\r
- } else {\r
- DVFS_DBG("%s,vd %s mode is not support now check\n", __FUNCTION__, vd->name);\r
-\r
+ if(vd->mode_flag>0)\r
+ {\r
+ DVFS_DBG("%s,vd %s mode(now is %d) support\n",__FUNCTION__,vd->name,vd->mode_flag);\r
}\r
+ else\r
+ {\r
+ DVFS_DBG("%s,vd %s mode is not support now check\n",__FUNCTION__,vd->name);\r
\r
+ }\r
+ \r
}\r
}\r
struct regulator *dvfs_get_regulator(char *regulator_name) \r
int dvfs_vd_clk_set_rate(struct clk *clk, unsigned long rate)\r
{\r
int ret = -1;\r
- struct clk_node *dvfs_info = clk_get_dvfs_info(clk);\r
-\r
+ struct clk_node *dvfs_info=clk_get_dvfs_info(clk);\r
+ \r
DVFS_DBG("%s(%s(%lu))\n", __func__, dvfs_info->name, rate);\r
\r
-#if 0 // judge by reference func in rk\r
- if (dvfs_support_clk_set_rate(dvfs_info) == false) {\r
+ #if 0 // judge by reference func in rk\r
+ if (dvfs_support_clk_set_rate(dvfs_info)==false) {\r
DVFS_ERR("dvfs func:%s is not support!\n", __func__);\r
return ret;\r
}\r
-#endif\r
-\r
- if(dvfs_info->vd && dvfs_info->vd->vd_dvfs_target) {\r
+ #endif\r
+ \r
+ if(dvfs_info->vd&&dvfs_info->vd->vd_dvfs_target){\r
// mutex_lock(&vd->dvfs_mutex);\r
mutex_lock(&rk_dvfs_mutex);\r
ret = dvfs_info->vd->vd_dvfs_target(clk, rate);\r
int dvfs_vd_clk_disable(struct clk *clk, int on)\r
{\r
int ret = -1;\r
- struct clk_node *dvfs_info = clk_get_dvfs_info(clk);\r
- DVFS_DBG("%s(%s(%s,%lu))\n", __func__, dvfs_info->name, DVFS_STR(on), clk_get_rate(clk));\r
+ struct clk_node *dvfs_info=clk_get_dvfs_info(clk); \r
+ DVFS_DBG("%s(%s(%s,%lu))\n", __func__, dvfs_info->name, DVFS_STR_DISABLE(on),clk_get_rate(clk));\r
\r
\r
-#if 0 // judge by reference func in rk\r
- if (dvfs_support_clk_disable(dvfs_info) == false) {\r
+ #if 0 // judge by reference func in rk\r
+ if (dvfs_support_clk_disable(dvfs_info)==false) {\r
DVFS_ERR("dvfs func:%s is not support!\n", __func__);\r
return ret;\r
}\r
-#endif\r
-\r
- if(dvfs_info->vd && dvfs_info->vd->vd_clk_disable_target) {\r
+ #endif\r
+ \r
+ if(dvfs_info->vd&&dvfs_info->vd->vd_clk_disable_target){\r
// mutex_lock(&vd->dvfs_mutex);\r
mutex_lock(&rk_dvfs_mutex);\r
ret = dvfs_info->vd->vd_clk_disable_target(clk, on);\r
mutex_unlock(&rk_dvfs_mutex);\r
// mutex_unlock(&vd->dvfs_mutex);\r
}\r
- DVFS_DBG("%s(%s(%s)),is end\n", __func__, dvfs_info->name, DVFS_STR(on));\r
+ DVFS_DBG("%s(%s(%lu)),is end\n", __func__, dvfs_info->name, DVFS_STR_ON(on));\r
\r
return ret;\r
}\r
return -1;\r
}\r
dvfs_clk = clk_get_dvfs_info(clk);\r
- if(!dvfs_clk) {\r
+ if(!dvfs_clk)\r
+ {\r
DVFS_ERR("%s is not a dvfs\n", __func__);\r
return -1;\r
}\r
\r
- DVFS_DBG("%s:clk=%s(%s),count=%d\n", __FUNCTION__, dvfs_clk->name,\r
- DVFS_STR(on), clk_used_count(clk));\r
- if(on) {\r
+ DVFS_DBG("%s:clk=%s(%s),count=%d\n",__FUNCTION__,dvfs_clk->name,\r
+ DVFS_STR_DISABLE,clk_used_count(clk));\r
+ if(on)\r
+ {\r
// enable ,is usecount =0,this time will set volt\r
- if(clk_used_count(clk) != 0)\r
+ if(clk_used_count(clk)!= 0)\r
return clk_set_enable_locked(clk, on);\r
- } else {\r
+ }\r
+ else\r
+ {\r
//disabe, is usecount =1,this time will set volt\r
- if(clk_used_count(clk) != 1)\r
+ if(clk_used_count(clk)!= 1)\r
return clk_set_enable_locked(clk, on);\r
}\r
if(!dvfs_clk->disable_ctr)\r
return clk_set_enable_locked(clk, on);\r
else\r
- disable_ctr = dvfs_clk->disable_ctr;\r
- if(on) {\r
- if(disable_ctr->delay && disable_ctr->disable_work_fn)\r
+ disable_ctr=dvfs_clk->disable_ctr;\r
+ if(on)\r
+ { \r
+ if(disable_ctr->delay&&disable_ctr->disable_work_fn)\r
cancel_delayed_work(&disable_ctr->disable_work);\r
- if(disable_ctr->clk_disable_target) {\r
- for(i = 0; i < 2; i++) {\r
+ if(disable_ctr->clk_disable_target)\r
+ {\r
+ for(i=0;i<2;i++)\r
+ {\r
ret = disable_ctr->clk_disable_target(clk, on);\r
- if(ret >= 0)\r
+ if(ret>=0)\r
break;\r
mdelay(1000);\r
}\r
- } else\r
- ret = 0;\r
-\r
+ }\r
+ else\r
+ ret=0;\r
+ \r
// volt resume fail, Muse set rate is mini\r
- if(ret < 0) {\r
- clk_set_rate_locked(clk, dvfs_clk->min_rate);\r
- DVFS_WARNING("%s:clk=%s enable set volt fail,set min rate\n", __FUNCTION__, dvfs_clk->name);\r
+ if(ret<0)\r
+ {\r
+ clk_set_rate_locked(clk,dvfs_clk->min_rate);\r
+ DVFS_WARNING("%s:clk=%s enable set volt fail,set min rate\n",__FUNCTION__,dvfs_clk->name);\r
}\r
}\r
\r
ret = clk_set_enable_locked(clk, on);\r
if(ret < 0)\r
- return ret;\r
- if(!on) {\r
- if(disable_ctr->delay && disable_ctr->disable_work_fn) {\r
- DVFS_DBG("%s:clk=%s disable delay=%d\n", __FUNCTION__, dvfs_clk->name, disable_ctr->delay);\r
- queue_delayed_work_on(0, dvfs_wq, &disable_ctr->disable_work,\r
- msecs_to_jiffies(disable_ctr->delay));\r
- } else {\r
- DVFS_DBG("%s:clk=%s disable now\n", __FUNCTION__, dvfs_clk->name);\r
+ return ret;\r
+ if(!on)\r
+ {\r
+ if(disable_ctr->delay&&disable_ctr->disable_work_fn)\r
+ {\r
+ DVFS_DBG("%s:clk=%s disable delay=%d\n",__FUNCTION__,dvfs_clk->name,disable_ctr->delay);\r
+ queue_delayed_work_on(0,dvfs_wq, &disable_ctr->disable_work, \r
+ msecs_to_jiffies(disable_ctr->delay));\r
+ }\r
+ else\r
+ {\r
+ DVFS_DBG("%s:clk=%s disable now\n",__FUNCTION__,dvfs_clk->name);\r
if(disable_ctr->clk_disable_target)\r
- ret = disable_ctr->clk_disable_target(clk, on);\r
+ ret=disable_ctr->clk_disable_target(clk, on);\r
}\r
}\r
return ret;\r
\r
void dvfs_clk_disable_delay_work(struct work_struct *work)\r
{\r
- struct clk_disable_ctr *disable_ctr = container_of(work, struct clk_disable_ctr, disable_work.work);\r
+ struct clk_disable_ctr *disable_ctr=container_of(work, struct clk_disable_ctr, disable_work.work);\r
struct clk_node *dvfs_clk;\r
if(!disable_ctr->dvfs_clk)\r
return;\r
- dvfs_clk = disable_ctr->dvfs_clk;\r
+ dvfs_clk=disable_ctr->dvfs_clk;\r
mutex_lock(&rk_dvfs_mutex);\r
- DVFS_DBG("%s:clk=%s disable delay work\n", __FUNCTION__, dvfs_clk->name);\r
- if(disable_ctr->clk_disable_target && (!clk_used_count(dvfs_clk->clk)))\r
- disable_ctr->clk_disable_target(dvfs_clk->clk, 0);\r
+ DVFS_DBG("%s:clk=%s disable delay work\n",__FUNCTION__,dvfs_clk->name);\r
+ if(disable_ctr->clk_disable_target&&(!clk_used_count(dvfs_clk->clk)))\r
+ disable_ctr->clk_disable_target(dvfs_clk->clk,0);\r
mutex_unlock(&rk_dvfs_mutex);\r
}\r
EXPORT_SYMBOL(dvfs_clk_disable_delay_work);\r
long temp_rate;\r
int rate;\r
int flags;\r
-\r
- if(!dvfs_clk->dvfs_table || dvfs_clk->clk == NULL || is_suport_round_rate(dvfs_clk->clk) < 0)\r
+ \r
+ if(!dvfs_clk->dvfs_table||dvfs_clk->clk==NULL||is_suport_round_rate(dvfs_clk->clk)<0)\r
return;\r
-\r
+ \r
mutex_lock(&mutex);\r
for (i = 0; (dvfs_clk->dvfs_table[i].frequency != CPUFREQ_TABLE_END); i++) {\r
//ddr rate = real rate+flags\r
- flags = dvfs_clk->dvfs_table[i].frequency % 1000;\r
- rate = (dvfs_clk->dvfs_table[i].frequency / 1000) * 1000;\r
- temp_rate = clk_round_rate(dvfs_clk->clk, rate * 1000);\r
- if(temp_rate <= 0) {\r
- DVFS_WARNING("clk %s:round_clk_rate : is %d,but round <=0", dvfs_clk->name, dvfs_clk->dvfs_table[i].frequency);\r
+ flags=dvfs_clk->dvfs_table[i].frequency%1000;\r
+ rate=(dvfs_clk->dvfs_table[i].frequency/1000)*1000;\r
+ temp_rate=clk_round_rate(dvfs_clk->clk,rate*1000);\r
+ if(temp_rate<=0)\r
+ { \r
+ DVFS_WARNING("clk %s:round_clk_rate : is %d,but round <=0",dvfs_clk->name,dvfs_clk->dvfs_table[i].frequency);\r
break;\r
}\r
- temp_rate = (temp_rate / 1000) + flags;\r
-\r
+ temp_rate=(temp_rate/1000)+flags;\r
+ \r
DVFS_DBG("clk %s round_clk_rate %d to %d\n",\r
- dvfs_clk->name, dvfs_clk->dvfs_table[i].frequency, (int)(temp_rate));\r
-\r
- dvfs_clk->dvfs_table[i].frequency = temp_rate;\r
+ dvfs_clk->name,dvfs_clk->dvfs_table[i].frequency,(int)(temp_rate));\r
+ \r
+ dvfs_clk->dvfs_table[i].frequency=temp_rate; \r
}\r
mutex_unlock(&mutex);\r
}\r
int dvfs_set_freq_volt_table(struct clk *clk, struct cpufreq_frequency_table *table)\r
{\r
struct clk_node *info = clk_get_dvfs_info(clk);\r
- int i = 0;\r
+ int i=0;\r
\r
if (!info)\r
- return -1;\r
- if (!table) {\r
- info->min_rate = 0;\r
- info->max_rate = 0;\r
+ return -1; \r
+ if (!table)\r
+ { \r
+ info->min_rate=0; \r
+ info->max_rate=0; \r
return -1;\r
}\r
\r
mutex_lock(&mutex);\r
info->dvfs_table = table;\r
- if(table[0].frequency != CPUFREQ_TABLE_END) {\r
+ if(table[0].frequency!= CPUFREQ_TABLE_END)\r
+ {\r
\r
- info->min_rate = (table[0].frequency / 1000) * 1000 * 1000; //to hz\r
- } else {\r
- info->min_rate = 0;\r
- info->max_rate = 0;\r
+ info->min_rate=(table[0].frequency/1000)*1000*1000;//to hz\r
+ }\r
+ else\r
+ {\r
+ info->min_rate=0; \r
+ info->max_rate=0; \r
return -1;\r
}\r
\r
- for(i = 0; table[i].frequency != CPUFREQ_TABLE_END; i++) {\r
-\r
- }\r
- info->max_rate = (table[i-1].frequency / 1000) * 1000 * 1000;\r
+ for(i=0;table[i].frequency!= CPUFREQ_TABLE_END;i++)\r
+ {\r
+ \r
+ } \r
+ info->max_rate=(table[i-1].frequency/1000)*1000*1000;\r
\r
- DVFS_DBG("%s,clk %s,limit max=%u,min=%u\n", __FUNCTION__, info->name, info->max_rate, info->min_rate);\r
+ DVFS_DBG("%s,clk %s,limit max=%lu,min=%lu\n",__FUNCTION__,info->name,info->max_rate,info->min_rate);\r
\r
mutex_unlock(&mutex);\r
dvfs_table_round_clk_rate(info);\r
return -1;\r
}\r
} else {\r
- clk_enable_dvfs_regulator_check(dvfs_clk->vd);\r
+ clk_enable_dvfs_regulator_check(dvfs_clk->vd);\r
// DVFS_DBG("%s(%s) vd volt=%u\n",__func__,dvfs_clk->name,dvfs_clk->vd->cur_volt);\r
}\r
\r
list_add(&vd->node, &rk_dvfs_tree);\r
INIT_LIST_HEAD(&vd->pd_list);\r
INIT_LIST_HEAD(&vd->req_volt_list);\r
- vd->mode_flag = 0;\r
- vd->volt_time_flag = 0;\r
- vd->n_voltages = 0;\r
+ vd->mode_flag=0;\r
+ vd->volt_time_flag=0;\r
+ vd->n_voltages=0;\r
mutex_unlock(&mutex);\r
return 0;\r
}\r
}\r
clk = dvfs_clk_get(NULL, dvfs_clk->name);\r
dvfs_clk->clk = clk;\r
- disable_ctr = dvfs_clk->disable_ctr;\r
- if(disable_ctr) {\r
- if(disable_ctr->clk_disable_target) {\r
- disable_ctr->dvfs_clk = dvfs_clk;\r
-\r
- if(disable_ctr->delay && disable_ctr->disable_work_fn) {\r
- INIT_DELAYED_WORK(&disable_ctr->disable_work, disable_ctr->disable_work_fn);\r
+ disable_ctr=dvfs_clk->disable_ctr;\r
+ if(disable_ctr)\r
+ {\r
+ if(disable_ctr->clk_disable_target)\r
+ {\r
+ disable_ctr->dvfs_clk=dvfs_clk;\r
+\r
+ if(disable_ctr->delay&&disable_ctr->disable_work_fn)\r
+ {\r
+ INIT_DELAYED_WORK(&disable_ctr->disable_work,disable_ctr->disable_work_fn); \r
}\r
- } else\r
- dvfs_clk->disable_ctr = NULL;\r
+ }else\r
+ dvfs_clk->disable_ctr=NULL;\r
}\r
clk_register_dvfs(dvfs_clk, clk);\r
INIT_LIST_HEAD(&dvfs_clk->depend_list);\r
int volt_pre = 0, volt_dep_pre = 0;\r
int ret = 0;\r
\r
- DVFS_DBG("ENTER %s, volt=%d(old=%d), volt_dep=%d(dep_old=%d)\n", __func__, \r
- volt_new, volt_old, volt_dep_new, volt_dep_old);\r
+ DVFS_DBG("ENTER %s, volt=%d(old=%d), volt_dep=%d(dep_old=%d)\n", __func__, volt_new, volt_old, volt_dep_new, volt_dep_old);\r
regulator = vd_clk->regulator;\r
regulator_dep = vd_dep->regulator;\r
\r
} else {\r
volt_dep = volt + dep_biger_than_clk;\r
}\r
- } else if (volt < volt_dep) {\r
+ } else if (volt < volt_dep){\r
if (volt == volt_new) {\r
volt_dep = volt + dep_biger_than_clk;\r
} else {\r
} else {\r
volt = volt_dep - dep_biger_than_clk;\r
}\r
- } else if (volt < volt_dep) {\r
+ } else if (volt < volt_dep){\r
if (volt_dep == volt_dep_new) {\r
volt = volt_dep - dep_biger_than_clk;\r
} else {\r
DVFS_DBG("\t\t%s:%d->%d\n", vd_clk->name, vd_clk->cur_volt, volt);\r
ret = dvfs_regulator_set_voltage_readback(regulator, volt, volt);\r
//udelay(get_volt_up_delay(volt, volt_pre));\r
- dvfs_volt_up_delay(vd_clk, volt, volt_pre);\r
+ dvfs_volt_up_delay(vd_clk,volt, volt_pre);\r
if (ret < 0) {\r
DVFS_ERR("%s %s set voltage up err ret = %d, Vnew = %d(was %d)mV\n",\r
__func__, vd_clk->name, ret, volt_new, volt_old);\r
DVFS_DBG("\t\t%s:%d->%d\n", vd_dep->name, vd_dep->cur_volt, volt_dep);\r
ret = dvfs_regulator_set_voltage_readback(regulator_dep, volt_dep, volt_dep);\r
//udelay(get_volt_up_delay(volt_dep, volt_dep_pre));\r
- dvfs_volt_up_delay(vd_dep, volt_dep, volt_dep_pre);\r
+ dvfs_volt_up_delay(vd_dep,volt_dep, volt_dep_pre);\r
if (ret < 0) {\r
DVFS_ERR("depend %s %s set voltage up err ret = %d, Vnew = %d(was %d)mV\n",\r
__func__, vd_dep->name, ret, volt_dep_new, volt_dep_old);\r
if (!IS_ERR_OR_NULL(vd_clk->regulator)) {\r
ret = dvfs_regulator_set_voltage_readback(vd_clk->regulator, volt_new, volt_new);\r
//udelay(get_volt_up_delay(volt_new, vd_clk->cur_volt));\r
- dvfs_volt_up_delay(vd_clk, volt_new, vd_clk->cur_volt);\r
+ dvfs_volt_up_delay(vd_clk,volt_new, vd_clk->cur_volt);\r
if (ret < 0) {\r
vd_clk->volt_set_flag = DVFS_SET_VOLT_FAILURE;\r
DVFS_ERR("%s %s set voltage up err ret = %d, Vnew = %d(was %d)mV\n",\r
DVFS_DBG("ENTER %s, volt=%d(old=%d) vd_dep=%d(dep_old=%d)\n", __func__,\r
volt_new, volt_old, volt_dep_new, volt_dep_old);\r
DVFS_DBG("ENTER %s, VOLT_DIFF: clk_cur=%d(clk_new=%d) dep_cur=%d(dep_new=%d)\n", __func__,\r
- cur_clk_biger_than_dep, new_clk_biger_than_dep,\r
+ cur_clk_biger_than_dep, new_clk_biger_than_dep, \r
cur_dep_biger_than_clk, new_dep_biger_than_clk);\r
\r
volt_new_corrected = volt_new;\r
volt_new_corrected = volt_new;\r
volt_dep_new_corrected = volt_dep_new;\r
correct_volt(&volt_new_corrected, &volt_dep_new_corrected, new_clk_biger_than_dep, new_dep_biger_than_clk);\r
- DVFS_DBG("last step to correct volt:\n");\r
+\r
if (vd_clk->cur_volt != volt_new_corrected) {\r
- DVFS_DBG("\t\t%s:%d->%d\n", vd_clk->name, vd_clk->cur_volt, volt_new_corrected);\r
+ DVFS_DBG("%s:%d->%d\n", vd_clk->name, vd_clk->cur_volt, volt_new_corrected);\r
ret = dvfs_regulator_set_voltage_readback(regulator, volt_new_corrected, volt_new_corrected);\r
//udelay(get_volt_up_delay(volt_new_corrected, vd_clk->cur_volt));\r
- dvfs_volt_up_delay(vd_clk, volt_new_corrected, vd_clk->cur_volt);\r
+ dvfs_volt_up_delay(vd_clk,volt_new_corrected, vd_clk->cur_volt);\r
if (ret < 0) {\r
DVFS_ERR("%s %s set voltage up err ret = %d, Vnew = %d(was %d)mV\n",\r
__func__, vd_clk->name, ret, volt_new_corrected, vd_clk->cur_volt);\r
vd_clk->cur_volt = volt_new_corrected;\r
}\r
if (vd_dep->cur_volt != volt_dep_new_corrected) {\r
- DVFS_DBG("\t\t%s:%d->%d\n", vd_dep->name, vd_dep->cur_volt, volt_dep_new_corrected);\r
+ DVFS_DBG("%s:%d->%d\n", vd_clk->name, vd_clk->cur_volt, volt_dep_new_corrected);\r
ret = dvfs_regulator_set_voltage_readback(regulator_dep, volt_dep_new_corrected, volt_dep_new_corrected);\r
//udelay(get_volt_up_delay(volt_dep_new_corrected, vd_dep->cur_volt));\r
- dvfs_volt_up_delay(vd_dep, volt_dep_new_corrected, vd_dep->cur_volt);\r
+ dvfs_volt_up_delay(vd_dep,volt_dep_new_corrected, vd_dep->cur_volt);\r
if (ret < 0) {\r
DVFS_ERR("depend %s %s set voltage up err ret = %d, Vnew = %d(was %d)mV\n",\r
__func__, vd_dep->name, ret, volt_dep_new_corrected, vd_dep->cur_volt);\r
}\r
}\r
printk( "-------------DVFS TREE END------------\n");\r
-\r
+ \r
mutex_unlock(&rk_dvfs_mutex);\r
return s - buf;\r
}\r
* AVS_BASE can use 172\r
*/\r
\r
-static struct avs_ctr_st *avs_ctr_data = NULL;\r
+static struct avs_ctr_st *avs_ctr_data=NULL;\r
#define init_avs_times 10\r
#define init_avs_st_num 5\r
\r
\r
void avs_board_init(struct avs_ctr_st *data)\r
{\r
-\r
- avs_ctr_data = data;\r
+ \r
+ avs_ctr_data=data;\r
}\r
void avs_init(void)\r
{\r
memset(&init_avs_paramet[0].is_set, 0, sizeof(init_avs_paramet));\r
- if(avs_ctr_data && avs_ctr_data->avs_init)\r
+ if(avs_ctr_data&&avs_ctr_data->avs_init)\r
avs_ctr_data->avs_init();\r
- avs_init_val_get(0, 1150000, "board_init");\r
+ avs_init_val_get(0,1150000,"board_init");\r
}\r
static u8 rk_get_avs_val(void)\r
{\r
-\r
- if(avs_ctr_data && avs_ctr_data->avs_get_val) {\r
+ \r
+ if(avs_ctr_data&&avs_ctr_data->avs_get_val)\r
+ { \r
return avs_ctr_data->avs_get_val();\r
}\r
return 0;\r
projects / firefly-linux-kernel-4.4.55.git / commitdiff