Expand i32/i64 CopyToReg f32/f64 to BIT_CONVERT + CopyToReg.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32493 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index c6ca13e2a38b2fe263a4b4dbfee15404936dfe0a..c112b873b7b5d0a8cbdae5422c2cbee9ec7a9f45 100644 (file)
--- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -3942,6 +3942,9 @@ SDOperand SelectionDAGLowering::CopyValueToVirtualRegister(Value *V,
     else
       Op = DAG.getNode(ISD::ANY_EXTEND, DestVT, Op);
     return DAG.getCopyToReg(getRoot(), Reg, Op);
+  } else if (SrcVT == MVT::f32 || SrcVT == MVT::f64) {
+    return DAG.getCopyToReg(getRoot(), Reg,
+                            DAG.getNode(ISD::BIT_CONVERT, DestVT, Op));
   } else  {
     // The src value is expanded into multiple registers.
     SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DestVT,