compare doubles

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30856 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp
index 559873389021dfdca78bc49fba784a14f38ec2a2..c27136c4730b9aa8e15d9ffdfdb1536ff3bb05bf 100644 (file)
--- a/lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp
@@ -539,10 +539,10 @@ static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG,
 static SDOperand GetCMP(ISD::CondCode CC, SDOperand LHS, SDOperand RHS,
                         SelectionDAG &DAG) {
   MVT::ValueType vt = LHS.getValueType();
-  assert(vt == MVT::i32 || vt == MVT::f32);
+  assert(vt == MVT::i32 || vt == MVT::f32 || vt == MVT::f64);
   //Note: unordered floating point compares should use a non throwing
   //compare.
-  bool isUnorderedFloat = vt == MVT::f32 &&
+  bool isUnorderedFloat = (vt == MVT::f32 || vt == MVT::f64) &&
     (CC >= ISD::SETUO && CC <= ISD::SETUNE);
   assert(!isUnorderedFloat && "Unordered float compares are not supported");
 

diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td
index 3371871a7c4daf5712c3c42971f8a597f8ca6212..45728ac607823f687b1e7f2c563fd02f431e384c 100644 (file)
--- a/lib/Target/ARM/ARMInstrInfo.td
+++ b/lib/Target/ARM/ARMInstrInfo.td
@@ -178,6 +178,10 @@ def fcmpes  : InstARM<(ops FPRegs:$a, FPRegs:$b),
                       "fcmpes $a, $b",
                       [(armcmp FPRegs:$a, FPRegs:$b)]>;
 
+def fcmped  : InstARM<(ops DFPRegs:$a, DFPRegs:$b),
+                      "fcmped $a, $b",
+                      [(armcmp DFPRegs:$a, DFPRegs:$b)]>;
+
 // Floating Point Conversion
 // We use bitconvert for moving the data between the register classes.
 // The format conversion is done with ARM specific nodes

diff --git a/test/CodeGen/ARM/fpcmp.ll b/test/CodeGen/ARM/fpcmp.ll
index 6d9012df41e53dd7db06afb90cf073a2d02b8eee..53529bcf04fd3d3ccaf53ca6353c5a7b478d78c2 100644 (file)
--- a/test/CodeGen/ARM/fpcmp.ll
+++ b/test/CodeGen/ARM/fpcmp.ll
@@ -3,7 +3,9 @@
 ; RUN: llvm-as < %s | llc -march=arm  | grep moveq &&
 ; RUN: llvm-as < %s | llc -march=arm  | grep movgt &&
 ; RUN: llvm-as < %s | llc -march=arm  | grep movge &&
-; RUN: llvm-as < %s | llc -march=arm  | grep movle
+; RUN: llvm-as < %s | llc -march=arm  | grep movle &&
+; RUN: llvm-as < %s | llc -march=arm  | grep fcmpes &&
+; RUN: llvm-as < %s | llc -march=arm  | grep fcmped
 
 int %f1(float %a) {
 entry:
@@ -39,3 +41,10 @@ entry:
        %tmp = cast bool %tmp to int            ; <int> [#uses=1]
        ret int %tmp
 }
+
+int %g1(double %a) {
+entry:
+       %tmp = setlt double %a, 1.000000e+00            ; <bool> [#uses=1]
+       %tmp = cast bool %tmp to int            ; <int> [#uses=1]
+       ret int %tmp
+}