def d : BaseSIMDScalarShift<U, opc, {1,?,?,?,?,?,?},
FPR64, FPR64, vecshiftL64, asm,
- [(set (v1i64 FPR64:$Rd), (OpNode (v1i64 FPR64:$Rn),
- (i32 vecshiftL64:$imm)))]> {
+ [(set (i64 FPR64:$Rd), (OpNode (i64 FPR64:$Rn), (i32 vecshiftL64:$imm)))]> {
let Inst{21-16} = imm{5-0};
}
+
+ def : Pat<(v1i64 (OpNode (v1i64 FPR64:$Rn), (i32 vecshiftL64:$imm))),
+ (!cast<Instruction>(NAME # "d") FPR64:$Rn, vecshiftL64:$imm)>;
}
multiclass SIMDScalarRShiftBHSD<bit U, bits<5> opc, string asm> {
--- /dev/null
+; RUN: llc < %s -verify-machineinstrs -march=arm64 | FileCheck %s
+
+; Check if sqshl/uqshl with constant shift amout can be selected.
+define i64 @test_vqshld_s64_i(i64 %a) {
+; CHECK-LABEL: test_vqshld_s64_i:
+; CHECK: sqshl {{d[0-9]+}}, {{d[0-9]+}}, #36
+ %1 = tail call i64 @llvm.arm64.neon.sqshl.i64(i64 %a, i64 36)
+ ret i64 %1
+}
+
+define i64 @test_vqshld_u64_i(i64 %a) {
+; CHECK-LABEL: test_vqshld_u64_i:
+; CHECK: uqshl {{d[0-9]+}}, {{d[0-9]+}}, #36
+ %1 = tail call i64 @llvm.arm64.neon.uqshl.i64(i64 %a, i64 36)
+ ret i64 %1
+}
+
+declare i64 @llvm.arm64.neon.uqshl.i64(i64, i64)
+declare i64 @llvm.arm64.neon.sqshl.i64(i64, i64)