enum VPU_CLIENT_TYPE type;
VPU_FREQ freq;
vpu_session *session;
+ struct vpu_subdev_data *data;
struct list_head session_link; /* link to vpu service session */
struct list_head status_link; /* link to register set list */
unsigned long size;
pservice->curr_mode = data->mode;
}
-static void vcodec_exit_mode(struct vpu_service_info *pservice)
+static void vcodec_exit_mode(struct vpu_subdev_data *data)
{
-
+ if (data->mmu_dev && test_bit(MMU_ACTIVATED, &data->state)) {
+ clear_bit(MMU_ACTIVATED, &data->state);
+ rockchip_iovmm_deactivate(data->dev);
+ data->pservice->curr_mode = VCODEC_RUNNING_MODE_NONE;
+ }
}
static int vpu_get_clk(struct vpu_service_info *pservice)
}
mem_region->hdl = hdl;
- vcodec_enter_mode(data);
ret = ion_map_iommu(data->dev, pservice->ion_client,
mem_region->hdl, &mem_region->iova, &mem_region->len);
- vcodec_exit_mode(pservice);
if (ret < 0) {
vpu_err("ion map iommu failed\n");
mem_region->hdl = hdl;
mem_region->reg_idx = tbl[i];
- vcodec_enter_mode(data);
ret = ion_map_iommu(data->dev,
pservice->ion_client,
mem_region->hdl,
&mem_region->iova,
&mem_region->len);
- vcodec_exit_mode(pservice);
if (ret < 0) {
dev_err(pservice->dev, "ion map iommu failed\n");
size = data->reg_size;
}
reg->session = session;
+ reg->data = data;
reg->type = session->type;
reg->size = size;
reg->freq = VPU_FREQ_DEFAULT;
reg->freq = VPU_FREQ_200M;
} else if (reg_check_fmt(reg) == VPU_DEC_FMT_H264) {
if (reg_probe_width(reg) > 3200) {
- // raise frequency for 4k avc.
+ /*raise frequency for 4k avc.*/
reg->freq = VPU_FREQ_500M;
}
} else {
list_del_init(®->session_link);
list_add_tail(®->session_link, ®->session->done);
- vcodec_enter_mode(data);
+ /*vcodec_enter_mode(data);*/
switch (reg->type) {
case VPU_ENC : {
pservice->reg_codec = NULL;
break;
}
}
- vcodec_exit_mode(pservice);
+ vcodec_exit_mode(data);
if (irq_reg != -1)
reg->reg[irq_reg] = pservice->irq_status;
}
}
- vcodec_exit_mode(pservice);
+ /*vcodec_exit_mode(data);*/
vpu_debug_leave();
}
}
if (can_set) {
reg_from_wait_to_run(pservice, reg);
- reg_copy_to_hw(data, reg);
+ reg_copy_to_hw(reg->data, reg);
}
}
vpu_debug_leave();
#ifdef CONFIG_COMPAT
.compat_ioctl = compat_vpu_service_ioctl,
#endif
- //.fasync = vpu_service_fasync,
};
static irqreturn_t vdpu_irq(int irq, void *dev_id);
atomic_set(&data->enc_dev.irq_count_pp, 0);
#if defined(CONFIG_VCODEC_MMU)
if (iommu_en) {
- vcodec_enter_mode(data);
if (data->mode == VCODEC_RUNNING_MODE_HEVC)
sprintf(mmu_dev_dts_name,
HEVC_IOMMU_COMPATIBLE_NAME);
rockchip_iovmm_set_fault_handler(dev, vcodec_sysmmu_fault_hdl);
}
#endif
+ vcodec_exit_mode(data);
/* create device node */
ret = alloc_chrdev_region(&data->dev_t, 0, 1, name);
if (ret) {
u32 raw_status;
u32 irq_status;
- vcodec_enter_mode(data);
+ /*vcodec_enter_mode(data);*/
irq_status = raw_status = readl(dev->hwregs + DEC_INTERRUPT_REGISTER);
pservice->irq_status = raw_status;
- vcodec_exit_mode(pservice);
+ /*vcodec_exit_mode(pservice);*/
- return IRQ_WAKE_THREAD;
+ if (atomic_read(&dev->irq_count_pp) ||
+ atomic_read(&dev->irq_count_codec))
+ return IRQ_WAKE_THREAD;
+ else
+ return IRQ_NONE;
}
static irqreturn_t vdpu_isr(int irq, void *dev_id)
vpu_device *dev = &data->enc_dev;
u32 irq_status;
- vcodec_enter_mode(data);
+ /*vcodec_enter_mode(data);*/
irq_status= readl(dev->hwregs + ENC_INTERRUPT_REGISTER);
pr_debug("vepu_irq irq status %x\n", irq_status);
pservice->irq_status = irq_status;
- vcodec_exit_mode(pservice);
+ /*vcodec_exit_mode(pservice);*/
- return IRQ_WAKE_THREAD;
+ if (atomic_read(&dev->irq_count_codec))
+ return IRQ_WAKE_THREAD;
+ else
+ return IRQ_NONE;
}
static irqreturn_t vepu_isr(int irq, void *dev_id)
{
int size = (len+15) & (~15);
struct ion_handle *handle;
- u8 *ptr;// = (u8*)kzalloc(size, GFP_KERNEL);
+ u8 *ptr;
if (ion_client == NULL)
ion_client = rockchip_ion_client_create("vcodec");
{
vpu_session session;
vpu_reg *reg;
- unsigned long size = 272;//sizeof(register_00); // registers array length
+ unsigned long size = 272;
int testidx = 0;
int ret = 0;
u8 *pps_tbl[TEST_CNT];