powerpc/dts: fix sRIO error interrupt for b4860
authorMinghuan Lian <Minghuan.Lian@freescale.com>
Wed, 31 Jul 2013 02:59:07 +0000 (10:59 +0800)
committerScott Wood <scottwood@freescale.com>
Tue, 29 Oct 2013 02:11:14 +0000 (21:11 -0500)
For B4 platform, MPIC EISR register is in reversed bitmap order,
instead of "Error interrupt source 0-31. Bit 0 represents SRC0."
the correct ordering is "Error interrupt source 0-31. Bit 0
represents SRC31." This patch is to fix sRIO EISR bit value
of error interrupt in dts node.

Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
arch/powerpc/boot/dts/fsl/b4860si-post.dtsi

index e5cf6c81dd6644bc8f4dc26c097102d5e5de3e65..981397518fc6243919e78118944d8dda2f763f6b 100644 (file)
@@ -41,7 +41,7 @@
 
 &rio {
        compatible = "fsl,srio";
-       interrupts = <16 2 1 11>;
+       interrupts = <16 2 1 20>;
        #address-cells = <2>;
        #size-cells = <2>;
        fsl,iommu-parent = <&pamu0>;