}
-int rk30_dvfs_init(void);
void __init rk30_clock_data_init(unsigned long gpll, unsigned long cpll, u32 flags)
{
_rk30_clock_data_init(gpll, cpll, flags);
- rk30_dvfs_init();
+ rk_dvfs_init();
}
/*
//cru_writel(0x07000000,CRU_MISC_CON);
}
-int rk30_dvfs_init(void);
+int rk_dvfs_init(void);
void __init rk30_clock_data_init(unsigned long gpll,unsigned long cpll,u32 flags)
{
_rk30_clock_data_init(gpll,cpll,flags);
- rk30_dvfs_init();
+ rk_dvfs_init();
}
/*
};\r
static struct avs_ctr_st rk30_avs_ctr;\r
\r
-int rk30_dvfs_init(void)\r
+int rk_dvfs_init(void)\r
{\r
int i = 0;\r
for (i = 0; i < ARRAY_SIZE(rk30_vds); i++) {\r
static inline struct regulator* dvfs_get_regulator(char *regulator_name){ return NULL; }\r
static inline int dvfs_clk_enable_limit(struct clk *clk, unsigned int min_rate, unsigned max_rate){ return 0; }\r
static inline int dvfs_clk_disable_limit(struct clk *clk){ return 0; };\r
-int dvfs_scale_volt_direct(struct vd_node *vd_clk, int volt_new){};\r
+static inline int dvfs_scale_volt_direct(struct vd_node *vd_clk, int volt_new){ return 0; };\r
\r
static inline void avs_init(void){};\r
static inline void avs_init_val_get(int index, int vol, char *s){};\r
static inline int avs_set_scal_val(u8 avs_base){ return 0; };\r
-void avs_board_init(struct avs_ctr_st *data){};\r
+static inline void avs_board_init(struct avs_ctr_st *data){};\r
#endif\r
\r
#endif\r