ARM64: dts: rockchip: rk3366: assign parent for i2s_src

As the 750MHz cpll can't produce accurate frequancy for i2s,
for example 11289600Hz, so assign their parents to the 576MHz gpll.

Change-Id: I430bce21ae69b47e561a95e691276d0c921a702c
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>

diff --git a/arch/arm64/boot/dts/rockchip/rk3366.dtsi b/arch/arm64/boot/dts/rockchip/rk3366.dtsi
index d10c0f5e12c7aa386f4caab011b4929d902cfe2b..44d0dacecf222d9139624b84a3dfa467eb168b4b 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3366.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3366.dtsi
@@ -734,6 +734,8 @@
                assigned-clocks =
                        <&cru SCLK_WIFIDSP>, <&cru SCLK_32K>,
                        <&cru DCLK_VOP_FULL>, <&cru DCLK_VOP_LITE>,
+                       <&cru SCLK_I2S_8CH_SRC>, <&cru SCLK_I2S_2CH_SRC>,
+                       <&cru SCLK_SPDIF_8CH_SRC>,
                        <&cru PLL_CPLL>, <&cru PLL_GPLL>,
                        <&cru PLL_NPLL>, <&cru PLL_MPLL>,
                        <&cru PLL_WPLL>, <&cru PLL_BPLL>,
@@ -744,6 +746,8 @@
                assigned-clock-rates =
                        <0>, <0>,
                        <0>, <0>,
+                       <0>, <0>,
+                       <0>,
                        <750000000>, <576000000>,
                        <594000000>, <594000000>,
                        <960000000>, <520000000>,
@@ -753,7 +757,9 @@
                        <144000000>;
                assigned-clock-parents =
                        <&cru SCLK_WIFI_WPLL>, <&cru SCLK_32K_INTR>,
-                       <&cru SCLK_MPLL_SRC>, <&cru PLL_NPLL>;
+                       <&cru SCLK_MPLL_SRC>, <&cru PLL_NPLL>,
+                       <&cru PLL_GPLL>, <&cru PLL_GPLL>,
+                       <&cru PLL_GPLL>;
        };
 
        grf: syscon@ff770000 {