-/*\r
- * drivers/video/rockchip/lcdc/rk3188_lcdc.c\r
- *\r
- * Copyright (C) 2013 ROCKCHIP, Inc.\r
- *Author:yxj<yxj@rock-chips.com>\r
- *This software is licensed under the terms of the GNU General Public\r
- * License version 2, as published by the Free Software Foundation, and\r
- * may be copied, distributed, and modified under those terms.\r
- *\r
- * This program is distributed in the hope that it will be useful,\r
- * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
- * GNU General Public License for more details.\r
- *\r
- */\r
-\r
-#include <linux/module.h>\r
-#include <linux/kernel.h>\r
-#include <linux/errno.h>\r
-#include <linux/string.h>\r
-#include <linux/mm.h>\r
-#include <linux/slab.h>\r
-#include <linux/device.h>\r
-#include <linux/delay.h>\r
-#include <linux/init.h>\r
-#include <linux/interrupt.h>\r
-#include <linux/platform_device.h>\r
-#include <linux/clk.h>\r
-#include <linux/earlysuspend.h>\r
-#include <asm/div64.h>\r
-#include <asm/uaccess.h>\r
-#include "rk3188_lcdc.h"\r
-\r
-\r
-\r
-static int dbg_thresd = 0;\r
-module_param(dbg_thresd, int, S_IRUGO|S_IWUSR);\r
-#define DBG(level,x...) do { \\r
- if(unlikely(dbg_thresd >= level)) \\r
- printk(KERN_INFO x);} while (0)\r
-\r
-//#define WAIT_FOR_SYNC 1\r
-static int rk3188_lcdc_clk_enable(struct rk3188_lcdc_device *lcdc_dev)\r
-{\r
-\r
- clk_enable(lcdc_dev->pd);\r
- clk_enable(lcdc_dev->hclk);\r
- clk_enable(lcdc_dev->dclk);\r
- clk_enable(lcdc_dev->aclk);\r
-\r
- spin_lock(&lcdc_dev->reg_lock);\r
- lcdc_dev->clk_on = 1;\r
- spin_unlock(&lcdc_dev->reg_lock);\r
- printk("rk3188 lcdc%d clk enable...\n",lcdc_dev->id);\r
- \r
- return 0;\r
-}\r
-\r
-static int rk3188_lcdc_clk_disable(struct rk3188_lcdc_device *lcdc_dev)\r
-{\r
- spin_lock(&lcdc_dev->reg_lock);\r
- lcdc_dev->clk_on = 0;\r
- spin_unlock(&lcdc_dev->reg_lock);\r
-\r
- clk_disable(lcdc_dev->dclk);\r
- clk_disable(lcdc_dev->hclk);\r
- clk_disable(lcdc_dev->aclk);\r
- clk_disable(lcdc_dev->pd);\r
- printk("rk3188 lcdc%d clk disable...\n",lcdc_dev->id);\r
- \r
- return 0;\r
-}\r
-\r
-static int rk3188_lcdc_resume_reg(struct rk3188_lcdc_device *lcdc_dev)\r
-{\r
- memcpy((u8*)lcdc_dev->regs, (u8*)lcdc_dev->regsbak, 0x84);\r
- return 0; \r
-}\r
-\r
-\r
-//enable layer,open:1,enable;0 disable\r
-static int win0_open(struct rk3188_lcdc_device *lcdc_dev,bool open)\r
-{\r
- spin_lock(&lcdc_dev->reg_lock);\r
- if(likely(lcdc_dev->clk_on))\r
- {\r
- if(open)\r
- {\r
- if(!lcdc_dev->atv_layer_cnt)\r
- {\r
- printk(KERN_INFO "lcdc%d wakeup from standby!\n",lcdc_dev->id);\r
- lcdc_msk_reg(lcdc_dev, SYS_CTRL,m_LCDC_STANDBY,v_LCDC_STANDBY(0));\r
- }\r
- lcdc_dev->atv_layer_cnt++;\r
- }\r
- else if((lcdc_dev->atv_layer_cnt > 0) && (!open))\r
- {\r
- lcdc_dev->atv_layer_cnt--;\r
- }\r
- lcdc_dev->driver.layer_par[0]->state = open;\r
-\r
- lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_WIN0_EN, v_WIN0_EN(open));\r
- if(!lcdc_dev->atv_layer_cnt) //if no layer used,disable lcdc\r
- {\r
- printk(KERN_INFO "no layer of lcdc%d is used,go to standby!\n",lcdc_dev->id);\r
- lcdc_msk_reg(lcdc_dev, SYS_CTRL,m_LCDC_STANDBY,v_LCDC_STANDBY(1));\r
- }\r
- lcdc_cfg_done(lcdc_dev); \r
- }\r
- spin_unlock(&lcdc_dev->reg_lock);\r
-\r
-\r
- return 0;\r
-}\r
-\r
-static int win1_open(struct rk3188_lcdc_device *lcdc_dev,bool open)\r
-{\r
- spin_lock(&lcdc_dev->reg_lock);\r
- if(likely(lcdc_dev->clk_on))\r
- {\r
- if(open)\r
- {\r
- if(!lcdc_dev->atv_layer_cnt)\r
- {\r
- printk(KERN_INFO "lcdc%d wakeup from standby!\n",lcdc_dev->id);\r
- lcdc_msk_reg(lcdc_dev, SYS_CTRL,m_LCDC_STANDBY,v_LCDC_STANDBY(0));\r
- }\r
- lcdc_dev->atv_layer_cnt++;\r
- }\r
- else if((lcdc_dev->atv_layer_cnt > 0) && (!open))\r
- {\r
- lcdc_dev->atv_layer_cnt--;\r
- }\r
- lcdc_dev->driver.layer_par[1]->state = open;\r
- \r
- lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_WIN1_EN, v_WIN1_EN(open));\r
- if(!lcdc_dev->atv_layer_cnt) //if no layer used,disable lcdc\r
- {\r
- printk(KERN_INFO "no layer of lcdc%d is used,go to standby!\n",lcdc_dev->id);\r
- lcdc_msk_reg(lcdc_dev, SYS_CTRL,m_LCDC_STANDBY,v_LCDC_STANDBY(1));\r
- }\r
- lcdc_cfg_done(lcdc_dev);\r
- }\r
- spin_unlock(&lcdc_dev->reg_lock);\r
- \r
- return 0;\r
-}\r
-\r
-static int rk3188_lcdc_open(struct rk_lcdc_device_driver *dev_drv,int layer_id,bool open)\r
-{\r
- int i=0;\r
- int __iomem *c;\r
- int v;\r
- struct rk3188_lcdc_device *lcdc_dev = \r
- container_of(dev_drv,struct rk3188_lcdc_device,driver);\r
-\r
- if((open) && (!lcdc_dev->atv_layer_cnt)) //enable clk,when first layer open\r
- {\r
- rk3188_lcdc_clk_enable(lcdc_dev);\r
- rk3188_lcdc_resume_reg(lcdc_dev); //resume reg\r
- spin_lock(&lcdc_dev->reg_lock);\r
- if(dev_drv->cur_screen->dsp_lut) //resume dsp lut\r
- {\r
- lcdc_msk_reg(lcdc_dev,SYS_CTRL,m_DSP_LUT_EN,v_DSP_LUT_EN(0));\r
- lcdc_cfg_done(lcdc_dev);\r
- mdelay(25); //wait for dsp lut disabled\r
- for(i=0;i<256;i++)\r
- {\r
- v = dev_drv->cur_screen->dsp_lut[i];\r
- c = lcdc_dev->dsp_lut_addr_base+i;\r
- writel_relaxed(v,c);\r
-\r
- }\r
- lcdc_msk_reg(lcdc_dev,SYS_CTRL,m_DSP_LUT_EN,v_DSP_LUT_EN(1)); //enable dsp lut\r
- }\r
- spin_unlock(&lcdc_dev->reg_lock);\r
- }\r
-\r
- if(layer_id == 0)\r
- {\r
- win0_open(lcdc_dev,open); \r
- }\r
- else if(layer_id == 1)\r
- {\r
- win1_open(lcdc_dev,open);\r
- }\r
- else \r
- {\r
- printk("invalid win number:%d\n",layer_id);\r
- }\r
-\r
- if((!open) && (!lcdc_dev->atv_layer_cnt)) //when all layer closed,disable clk\r
- {\r
- rk3188_lcdc_clk_disable(lcdc_dev);\r
- }\r
-\r
- printk(KERN_INFO "lcdc%d win%d %s,atv layer:%d\n",\r
- lcdc_dev->id,layer_id,open?"open":"closed",\r
- lcdc_dev->atv_layer_cnt);\r
- return 0;\r
-}\r
-\r
-static int rk3188_lcdc_init(struct rk_lcdc_device_driver *dev_drv)\r
-{\r
- int i = 0;\r
- int __iomem *c;\r
- int v;\r
- struct rk3188_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk3188_lcdc_device,driver);\r
- if(lcdc_dev->id == 0) //lcdc0\r
- {\r
- lcdc_dev->pd = clk_get(NULL,"pd_lcdc0");\r
- lcdc_dev->hclk = clk_get(NULL,"hclk_lcdc0"); \r
- lcdc_dev->aclk = clk_get(NULL,"aclk_lcdc0");\r
- lcdc_dev->dclk = clk_get(NULL,"dclk_lcdc0");\r
- }\r
- else if(lcdc_dev->id == 1)\r
- {\r
- lcdc_dev->pd = clk_get(NULL,"pd_lcdc1");\r
- lcdc_dev->hclk = clk_get(NULL,"hclk_lcdc1"); \r
- lcdc_dev->aclk = clk_get(NULL,"aclk_lcdc1");\r
- lcdc_dev->dclk = clk_get(NULL,"dclk_lcdc1");\r
- }\r
- else\r
- {\r
- printk(KERN_ERR "invalid lcdc device!\n");\r
- return -EINVAL;\r
- }\r
- if (IS_ERR(lcdc_dev->pd) || (IS_ERR(lcdc_dev->aclk)) ||(IS_ERR(lcdc_dev->dclk)) || (IS_ERR(lcdc_dev->hclk)))\r
- {\r
- printk(KERN_ERR "failed to get lcdc%d clk source\n",lcdc_dev->id);\r
- }\r
- \r
- rk3188_lcdc_clk_enable(lcdc_dev);\r
- \r
- lcdc_set_bit(lcdc_dev,SYS_CTRL,m_AUTO_GATING_EN);//eanble axi-clk auto gating for low power\r
- if(dev_drv->cur_screen->dsp_lut)\r
- {\r
- lcdc_msk_reg(lcdc_dev,SYS_CTRL,m_DSP_LUT_EN,v_DSP_LUT_EN(0));\r
- lcdc_cfg_done(lcdc_dev);\r
- msleep(25);\r
- for(i=0;i<256;i++)\r
- {\r
- v = dev_drv->cur_screen->dsp_lut[i];\r
- c = lcdc_dev->dsp_lut_addr_base+i;\r
- writel_relaxed(v,c);\r
- \r
- }\r
- lcdc_msk_reg(lcdc_dev,SYS_CTRL,m_DSP_LUT_EN,v_DSP_LUT_EN(1));\r
- }\r
- \r
- lcdc_cfg_done(lcdc_dev); // write any value to REG_CFG_DONE let config become effective\r
-\r
- rk3188_lcdc_clk_disable(lcdc_dev);\r
- \r
- return 0;\r
-}\r
-\r
-\r
-//set lcdc according the screen info\r
-static int rk3188_load_screen(struct rk_lcdc_device_driver *dev_drv, bool initscreen)\r
-{\r
- int ret = -EINVAL;\r
- int fps;\r
- u16 face = 0;\r
- struct rk3188_lcdc_device *lcdc_dev = \r
- container_of(dev_drv,struct rk3188_lcdc_device,driver);\r
- rk_screen *screen = dev_drv->cur_screen;\r
- u16 right_margin = screen->right_margin;\r
- u16 left_margin = screen->left_margin;\r
- u16 lower_margin = screen->lower_margin;\r
- u16 upper_margin = screen->upper_margin;\r
- u16 x_res = screen->x_res;\r
- u16 y_res = screen->y_res;\r
-\r
- \r
- spin_lock(&lcdc_dev->reg_lock);\r
- if(likely(lcdc_dev->clk_on))\r
- {\r
- if(screen->type==SCREEN_MCU)\r
- {\r
- printk("MUC¡¡screen not supported now!\n");\r
- return -EINVAL;\r
- }\r
-\r
- switch (screen->face)\r
- {\r
- case OUT_P565:\r
- face = OUT_P565; //dither down to rgb565\r
- lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE, v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(0));\r
- break;\r
- case OUT_P666:\r
- face = OUT_P666; //dither down to rgb666\r
- lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE, v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(1));\r
- break;\r
- case OUT_D888_P565:\r
- face = OUT_P888;\r
- lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE, v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(0));\r
- break;\r
- case OUT_D888_P666:\r
- face = OUT_P888;\r
- lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE, v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(1));\r
- break;\r
- case OUT_P888:\r
- face = OUT_P888;\r
- break;\r
- default:\r
- printk("unsupported display output interface!\n");\r
- break;\r
- }\r
-\r
- //use default overlay,set vsyn hsync den dclk polarity\r
- lcdc_msk_reg(lcdc_dev, DSP_CTRL0,m_DSP_OUT_FORMAT | m_HSYNC_POL | m_VSYNC_POL |\r
- m_DEN_POL |m_DCLK_POL,v_DSP_OUT_FORMAT(face) | v_HSYNC_POL(screen->pin_hsync) | \r
- v_VSYNC_POL(screen->pin_vsync) | v_DEN_POL(screen->pin_den) | v_DCLK_POL(screen->pin_dclk));\r
-\r
- \r
- //set background color to black,set swap according to the screen panel,disable blank mode\r
- lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_BG_COLOR| m_DSP_BG_SWAP | m_DSP_RB_SWAP | \r
- m_DSP_RG_SWAP | m_DSP_DELTA_SWAP | m_DSP_DUMMY_SWAP | m_BLANK_EN,\r
- v_BG_COLOR(0x000000) | v_DSP_BG_SWAP(screen->swap_gb) | \r
- v_DSP_RB_SWAP(screen->swap_rb) | v_DSP_RG_SWAP(screen->swap_rg) | \r
- v_DSP_DELTA_SWAP(screen->swap_delta) | v_DSP_DUMMY_SWAP(screen->swap_dumy) |\r
- v_BLANK_EN(0) | v_BLACK_EN(0));\r
- lcdc_writel(lcdc_dev,DSP_HTOTAL_HS_END,v_HSYNC(screen->hsync_len) |\r
- v_HORPRD(screen->hsync_len + left_margin + x_res + right_margin));\r
- lcdc_writel(lcdc_dev,DSP_HACT_ST_END,v_HAEP(screen->hsync_len + left_margin + x_res) |\r
- v_HASP(screen->hsync_len + left_margin));\r
-\r
- lcdc_writel(lcdc_dev,DSP_VTOTAL_VS_END, v_VSYNC(screen->vsync_len) |\r
- v_VERPRD(screen->vsync_len + upper_margin + y_res + lower_margin));\r
- lcdc_writel(lcdc_dev,DSP_VACT_ST_END,v_VAEP(screen->vsync_len + upper_margin+y_res)|\r
- v_VASP(screen->vsync_len + screen->upper_margin));\r
- }\r
- spin_unlock(&lcdc_dev->reg_lock);\r
-\r
- ret = clk_set_rate(lcdc_dev->dclk, screen->pixclock);\r
- if(ret)\r
- {\r
- dev_err(dev_drv->dev,"set lcdc%d dclk failed\n",lcdc_dev->id);\r
- }\r
- lcdc_dev->driver.pixclock = lcdc_dev->pixclock = div_u64(1000000000000llu, clk_get_rate(lcdc_dev->dclk));\r
- \r
- fps = rk_fb_calc_fps(screen,lcdc_dev->pixclock);\r
- screen->ft = 1000/fps;\r
- printk("%s: dclk:%lu>>fps:%d ",lcdc_dev->driver.name,clk_get_rate(lcdc_dev->dclk),fps);\r
-\r
- if(screen->init)\r
- {\r
- screen->init();\r
- }\r
- \r
- dev_info(dev_drv->dev,"%s for lcdc%d ok!\n",__func__,lcdc_dev->id);\r
- return 0;\r
-}\r
-\r
-\r
-static int win0_set_par(struct rk3188_lcdc_device *lcdc_dev,rk_screen *screen,\r
- struct layer_par *par )\r
-{\r
- u32 xact, yact, xvir, yvir, xpos, ypos;\r
- u32 ScaleYrgbX = 0x1000;\r
- u32 ScaleYrgbY = 0x1000;\r
- u32 ScaleCbrX = 0x1000;\r
- u32 ScaleCbrY = 0x1000;\r
-\r
- xact = par->xact; //active (origin) picture window width/height \r
- yact = par->yact;\r
- xvir = par->xvir; // virtual resolution \r
- yvir = par->yvir;\r
- xpos = par->xpos+screen->left_margin + screen->hsync_len;\r
- ypos = par->ypos+screen->upper_margin + screen->vsync_len;\r
-\r
- \r
- ScaleYrgbX = CalScale(xact, par->xsize); //both RGB and yuv need this two factor\r
- ScaleYrgbY = CalScale(yact, par->ysize);\r
- switch (par->format)\r
- {\r
- case YUV422:// yuv422\r
- ScaleCbrX = CalScale((xact/2), par->xsize);\r
- ScaleCbrY = CalScale(yact, par->ysize);\r
- break;\r
- case YUV420: // yuv420\r
- ScaleCbrX = CalScale(xact/2, par->xsize);\r
- ScaleCbrY = CalScale(yact/2, par->ysize);\r
- break;\r
- case YUV444:// yuv444\r
- ScaleCbrX = CalScale(xact, par->xsize);\r
- ScaleCbrY = CalScale(yact, par->ysize);\r
- break;\r
- default:\r
- break;\r
- }\r
-\r
- DBG(1,"%s for lcdc%d>>format:%d>>>xact:%d>>yact:%d>>xsize:%d>>ysize:%d>>xvir:%d>>yvir:%d>>xpos:%d>>ypos:%d>>\n",\r
- __func__,lcdc_dev->id,par->format,xact,yact,par->xsize,par->ysize,xvir,yvir,xpos,ypos);\r
- \r
- spin_lock(&lcdc_dev->reg_lock);\r
- if(likely(lcdc_dev->clk_on))\r
- {\r
- lcdc_writel(lcdc_dev,WIN0_SCL_FACTOR_YRGB,v_X_SCL_FACTOR(ScaleYrgbX) | v_Y_SCL_FACTOR(ScaleYrgbY));\r
- lcdc_writel(lcdc_dev,WIN0_SCL_FACTOR_CBR,v_X_SCL_FACTOR(ScaleCbrX) | v_Y_SCL_FACTOR(ScaleCbrY));\r
- lcdc_msk_reg(lcdc_dev,SYS_CTRL,m_WIN0_FORMAT,v_WIN0_FORMAT(par->format)); //(inf->video_mode==0)\r
- lcdc_writel(lcdc_dev,WIN0_ACT_INFO,v_ACT_WIDTH(xact) | v_ACT_HEIGHT(yact));\r
- lcdc_writel(lcdc_dev,WIN0_DSP_ST,v_DSP_STX(xpos) | v_DSP_STY(ypos));\r
- lcdc_writel(lcdc_dev,WIN0_DSP_INFO,v_DSP_WIDTH(par->xsize) | v_DSP_HEIGHT(par->ysize));\r
- lcdc_msk_reg(lcdc_dev,WIN0_COLOR_KEY,m_COLOR_KEY_EN,v_COLOR_KEY_EN(0));\r
- \r
- switch(par->format) \r
- {\r
- case ARGB888:\r
- lcdc_msk_reg(lcdc_dev, WIN_VIR,m_WIN0_VIR,v_ARGB888_VIRWIDTH(xvir));\r
- //lcdc_msk_reg(lcdc_dev,SYS_CTRL1,m_W0_RGB_RB_SWAP,v_W0_RGB_RB_SWAP(1));\r
- break;\r
- case RGB888: //rgb888\r
- lcdc_msk_reg(lcdc_dev, WIN_VIR,m_WIN0_VIR,v_RGB888_VIRWIDTH(xvir));\r
- //lcdc_msk_reg(lcdc_dev,SYS_CTRL1,m_W0_RGB_RB_SWAP,v_W0_RGB_RB_SWAP(1));\r
- break;\r
- case RGB565: //rgb565\r
- lcdc_msk_reg(lcdc_dev, WIN_VIR,m_WIN0_VIR,v_RGB565_VIRWIDTH(xvir));\r
- break;\r
- case YUV422:\r
- case YUV420:\r
- case YUV444:\r
- lcdc_msk_reg(lcdc_dev, WIN_VIR,m_WIN0_VIR,v_YUV_VIRWIDTH(xvir));\r
- break;\r
- default:\r
- dev_err(lcdc_dev->driver.dev,"un supported format!\n");\r
- break;\r
- }\r
-\r
- }\r
- spin_unlock(&lcdc_dev->reg_lock);\r
-\r
- return 0;\r
-\r
-}\r
-\r
-static int win1_set_par(struct rk3188_lcdc_device *lcdc_dev,rk_screen *screen,\r
- struct layer_par *par )\r
-{\r
- u32 xact, yact, xvir, yvir, xpos, ypos;\r
-\r
- xact = par->xact; \r
- yact = par->yact;\r
- xvir = par->xvir; \r
- yvir = par->yvir;\r
- xpos = par->xpos+screen->left_margin + screen->hsync_len;\r
- ypos = par->ypos+screen->upper_margin + screen->vsync_len;\r
-\r
- \r
- DBG(1,"%s for lcdc%d>>format:%d>>>xact:%d>>yact:%d>>xsize:%d>>ysize:%d>>xvir:%d>>yvir:%d>>xpos:%d>>ypos:%d>>\n",\r
- __func__,lcdc_dev->id,par->format,xact,yact,par->xsize,par->ysize,xvir,yvir,xpos,ypos);\r
-\r
- \r
- spin_lock(&lcdc_dev->reg_lock);\r
- if(likely(lcdc_dev->clk_on))\r
- {\r
- lcdc_msk_reg(lcdc_dev,SYS_CTRL,m_WIN1_FORMAT, v_WIN1_FORMAT(par->format));\r
- lcdc_writel(lcdc_dev, WIN1_DSP_INFO,v_DSP_WIDTH(par->xsize) | v_DSP_HEIGHT(par->ysize));\r
- lcdc_writel(lcdc_dev, WIN1_DSP_ST,v_DSP_STX(xpos) | v_DSP_STY(ypos));\r
- // disable win1 color key and set the color to black(rgb=0)\r
- lcdc_msk_reg(lcdc_dev, WIN1_COLOR_KEY,m_COLOR_KEY_EN,v_COLOR_KEY_EN(0));\r
- switch(par->format)\r
- {\r
- case ARGB888:\r
- lcdc_msk_reg(lcdc_dev, WIN_VIR,m_WIN1_VIR,v_WIN1_ARGB888_VIRWIDTH(xvir));\r
- //lcdc_msk_reg(lcdc_dev,SYS_CTRL1,m_W1_RGB_RB_SWAP,v_W1_RGB_RB_SWAP(1));\r
- break;\r
- case RGB888: //rgb888\r
- lcdc_msk_reg(lcdc_dev, WIN_VIR,m_WIN1_VIR,v_WIN1_RGB888_VIRWIDTH(xvir));\r
- // lcdc_msk_reg(lcdc_dev,SYS_CTRL1,m_W1_RGB_RB_SWAP,v_W1_RGB_RB_SWAP(1));\r
- break;\r
- case RGB565: //rgb565\r
- lcdc_msk_reg(lcdc_dev, WIN_VIR,m_WIN1_VIR,v_WIN1_RGB565_VIRWIDTH(xvir));\r
- break;\r
- default:\r
- dev_err(lcdc_dev->driver.dev,"un supported format!\n");\r
- break;\r
- }\r
-\r
- }\r
- spin_unlock(&lcdc_dev->reg_lock);\r
-\r
- return 0;\r
-}\r
-\r
-\r
-static int rk3188_lcdc_set_par(struct rk_lcdc_device_driver *dev_drv,int layer_id)\r
-{\r
- struct rk3188_lcdc_device *lcdc_dev = \r
- container_of(dev_drv,struct rk3188_lcdc_device,driver);\r
- struct layer_par *par = NULL;\r
- rk_screen *screen = dev_drv->cur_screen;\r
-\r
- if(!screen)\r
- {\r
- dev_err(dev_drv->dev,"screen is null!\n");\r
- return -ENOENT;\r
- }\r
- if(layer_id==0)\r
- {\r
- par = dev_drv->layer_par[0];\r
- win0_set_par(lcdc_dev,screen,par);\r
- }\r
- else if(layer_id==1)\r
- {\r
- par = dev_drv->layer_par[1];\r
- win1_set_par(lcdc_dev,screen,par);\r
- }\r
- else\r
- {\r
- dev_err(dev_drv->dev,"unsupported win number:%d\n",layer_id);\r
- return -EINVAL;\r
- }\r
- \r
- return 0;\r
-}\r
-\r
-static int win0_display(struct rk3188_lcdc_device *lcdc_dev,struct layer_par *par )\r
-{\r
- u32 y_addr;\r
- u32 uv_addr;\r
- y_addr = par->smem_start + par->y_offset;\r
- uv_addr = par->cbr_start + par->c_offset;\r
- DBG(2,KERN_INFO "lcdc%d>>%s:y_addr:0x%x>>uv_addr:0x%x\n",lcdc_dev->id,__func__,y_addr,uv_addr);\r
-\r
- spin_lock(&lcdc_dev->reg_lock);\r
- if(likely(lcdc_dev->clk_on))\r
- {\r
- lcdc_writel(lcdc_dev, WIN0_YRGB_MST0, y_addr);\r
- lcdc_writel(lcdc_dev, WIN0_CBR_MST0, uv_addr);\r
- lcdc_cfg_done(lcdc_dev);\r
- }\r
- spin_unlock(&lcdc_dev->reg_lock);\r
-\r
- return 0;\r
- \r
-}\r
-\r
-static int win1_display(struct rk3188_lcdc_device *lcdc_dev,struct layer_par *par )\r
-{\r
- u32 y_addr;\r
- u32 uv_addr;\r
- y_addr = par->smem_start + par->y_offset;\r
- uv_addr = par->cbr_start + par->c_offset;\r
- DBG(2,KERN_INFO "lcdc%d>>%s>>y_addr:0x%x>>uv_addr:0x%x\n",lcdc_dev->id,__func__,y_addr,uv_addr);\r
-\r
- spin_lock(&lcdc_dev->reg_lock);\r
- if(likely(lcdc_dev->clk_on))\r
- {\r
- lcdc_writel(lcdc_dev,WIN1_MST,y_addr);\r
- lcdc_cfg_done(lcdc_dev); \r
- }\r
- spin_unlock(&lcdc_dev->reg_lock);\r
-\r
- return 0;\r
-}\r
-\r
-static int rk3188_lcdc_pan_display(struct rk_lcdc_device_driver * dev_drv,int layer_id)\r
-{\r
- struct rk3188_lcdc_device *lcdc_dev = \r
- container_of(dev_drv,struct rk3188_lcdc_device,driver);\r
- struct layer_par *par = NULL;\r
- rk_screen *screen = dev_drv->cur_screen;\r
- unsigned long flags;\r
- int timeout;\r
- \r
- if(!screen)\r
- {\r
- dev_err(dev_drv->dev,"screen is null!\n");\r
- return -ENOENT; \r
- }\r
- if(layer_id==0)\r
- {\r
- par = dev_drv->layer_par[0];\r
- win0_display(lcdc_dev,par);\r
- }\r
- else if(layer_id==1)\r
- {\r
- par = dev_drv->layer_par[1];\r
- win1_display(lcdc_dev,par);\r
- }\r
- else \r
- {\r
- dev_err(dev_drv->dev,"invalid win number:%d!\n",layer_id);\r
- return -EINVAL;\r
- }\r
- if((dev_drv->first_frame)) //this is the first frame of the system ,enable frame start interrupt\r
- {\r
- dev_drv->first_frame = 0;\r
- lcdc_msk_reg(lcdc_dev,INT_STATUS,m_FS_INT_CLEAR |m_FS_INT_EN ,\r
- v_FS_INT_CLEAR(1) | v_FS_INT_EN(1));\r
- lcdc_cfg_done(lcdc_dev); // write any value to REG_CFG_DONE let config become effective\r
- \r
- }\r
-\r
-#if defined(WAIT_FOR_SYNC)\r
- spin_lock_irqsave(&dev_drv->cpl_lock,flags);\r
- init_completion(&dev_drv->frame_done);\r
- spin_unlock_irqrestore(&dev_drv->cpl_lock,flags);\r
- timeout = wait_for_completion_timeout(&dev_drv->frame_done,msecs_to_jiffies(dev_drv->cur_screen->ft+5));\r
- if(!timeout&&(!dev_drv->frame_done.done))\r
- {\r
- printk(KERN_ERR "wait for new frame start time out!\n");\r
- return -ETIMEDOUT;\r
- }\r
-#endif\r
- return 0;\r
-}\r
-\r
-static int rk3188_lcdc_blank(struct rk_lcdc_device_driver *dev_drv,\r
- int layer_id,int blank_mode)\r
-{\r
- return 0;\r
-}\r
-\r
-\r
-static int rk3188_lcdc_ioctl(struct rk_lcdc_device_driver *dev_drv, unsigned int cmd,unsigned long arg,int layer_id)\r
-{\r
- return 0;\r
-}\r
-\r
-static int rk3188_lcdc_early_suspend(struct rk_lcdc_device_driver *dev_drv)\r
-{\r
- return 0;\r
-}\r
-\r
-static int rk3188_lcdc_early_resume(struct rk_lcdc_device_driver *dev_drv)\r
-{\r
- return 0;\r
-}\r
-\r
-static int rk3188_lcdc_get_layer_state(struct rk_lcdc_device_driver *dev_drv,int layer_id)\r
-{\r
- return 0;\r
-}\r
-\r
-static int rk3188_lcdc_ovl_mgr(struct rk_lcdc_device_driver *dev_drv,int swap,bool set)\r
-{\r
- return 0;\r
-}\r
-\r
-static ssize_t rk3188_lcdc_get_disp_info(struct rk_lcdc_device_driver *dev_drv,char *buf,int layer_id)\r
-{\r
- return 0;\r
-}\r
-\r
-static int rk3188_lcdc_fps_mgr(struct rk_lcdc_device_driver *dev_drv,int fps,bool set)\r
-{\r
- return 0;\r
-}\r
-\r
-\r
-static int rk3188_fb_layer_remap(struct rk_lcdc_device_driver *dev_drv,\r
- enum fb_win_map_order order)\r
-{\r
- mutex_lock(&dev_drv->fb_win_id_mutex);\r
- if(order == FB_DEFAULT_ORDER )\r
- {\r
- order = FB0_WIN0_FB1_WIN1_FB2_WIN2;\r
- }\r
- dev_drv->fb2_win_id = order/100;\r
- dev_drv->fb1_win_id = (order/10)%10;\r
- dev_drv->fb0_win_id = order%10;\r
- mutex_unlock(&dev_drv->fb_win_id_mutex);\r
-\r
- printk("fb0:win%d\nfb1:win%d\nfb2:win%d\n",dev_drv->fb0_win_id,dev_drv->fb1_win_id,\r
- dev_drv->fb2_win_id);\r
-\r
- return 0;\r
-}\r
-\r
-static int rk3188_fb_get_layer(struct rk_lcdc_device_driver *dev_drv,const char *id)\r
-{\r
- int layer_id = 0;\r
- mutex_lock(&dev_drv->fb_win_id_mutex);\r
- if(!strcmp(id,"fb0")||!strcmp(id,"fb2"))\r
- {\r
- layer_id = dev_drv->fb0_win_id;\r
- }\r
- else if(!strcmp(id,"fb1")||!strcmp(id,"fb3"))\r
- {\r
- layer_id = dev_drv->fb1_win_id;\r
- }\r
- mutex_unlock(&dev_drv->fb_win_id_mutex);\r
-\r
- return layer_id;\r
-}\r
-\r
-static int rk3188_set_dsp_lut(struct rk_lcdc_device_driver *dev_drv,int *lut)\r
-{\r
- int i=0;\r
- int __iomem *c;\r
- int v;\r
- int ret = 0;\r
-\r
- struct rk3188_lcdc_device *lcdc_dev = \r
- container_of(dev_drv,struct rk3188_lcdc_device,driver);\r
- lcdc_msk_reg(lcdc_dev,SYS_CTRL,m_DSP_LUT_EN,v_DSP_LUT_EN(0));\r
- lcdc_cfg_done(lcdc_dev);\r
- msleep(25);\r
- if(dev_drv->cur_screen->dsp_lut)\r
- {\r
- for(i=0;i<256;i++)\r
- {\r
- v = dev_drv->cur_screen->dsp_lut[i] = lut[i];\r
- c = lcdc_dev->dsp_lut_addr_base+i;\r
- writel_relaxed(v,c);\r
- \r
- }\r
- }\r
- else\r
- {\r
- dev_err(dev_drv->dev,"no buffer to backup lut data!\n");\r
- ret = -1;\r
- }\r
- lcdc_msk_reg(lcdc_dev,SYS_CTRL,m_DSP_LUT_EN,v_DSP_LUT_EN(1));\r
- lcdc_cfg_done(lcdc_dev);\r
-\r
- return ret;\r
-}\r
-\r
-static struct layer_par lcdc_layer[] = {\r
- [0] = {\r
- .name = "win0",\r
- .id = 0,\r
- .support_3d = true,\r
- },\r
- [1] = {\r
- .name = "win1",\r
- .id = 1,\r
- .support_3d = false,\r
- },\r
-};\r
-\r
-static struct rk_lcdc_device_driver lcdc_driver = {\r
- .name = "lcdc",\r
- .def_layer_par = lcdc_layer,\r
- .num_layer = ARRAY_SIZE(lcdc_layer),\r
- .open = rk3188_lcdc_open,\r
- .init_lcdc = rk3188_lcdc_init,\r
- .load_screen = rk3188_load_screen,\r
- .set_par = rk3188_lcdc_set_par,\r
- .pan_display = rk3188_lcdc_pan_display,\r
- .blank = rk3188_lcdc_blank,\r
- .ioctl = rk3188_lcdc_ioctl,\r
- .suspend = rk3188_lcdc_early_suspend,\r
- .resume = rk3188_lcdc_early_resume,\r
- .get_layer_state = rk3188_lcdc_get_layer_state,\r
- .ovl_mgr = rk3188_lcdc_ovl_mgr,\r
- .get_disp_info = rk3188_lcdc_get_disp_info,\r
- .fps_mgr = rk3188_lcdc_fps_mgr,\r
- .fb_get_layer = rk3188_fb_get_layer,\r
- .fb_layer_remap = rk3188_fb_layer_remap,\r
- .set_dsp_lut = rk3188_set_dsp_lut,\r
-};\r
-\r
-static irqreturn_t rk3188_lcdc_isr(int irq, void *dev_id)\r
-{\r
- struct rk3188_lcdc_device *lcdc_dev = \r
- (struct rk3188_lcdc_device *)dev_id;\r
- \r
- lcdc_msk_reg(lcdc_dev, INT_STATUS, m_FS_INT_CLEAR, v_FS_INT_CLEAR(1));\r
-\r
-#if defined(WAIT_FOR_SYNC)\r
- if(lcdc_dev->driver.num_buf < 3) //three buffer ,no need to wait for sync\r
- {\r
- spin_lock(&(lcdc_dev->driver.cpl_lock));\r
- complete(&(lcdc_dev->driver.frame_done));\r
- spin_unlock(&(lcdc_dev->driver.cpl_lock));\r
- }\r
-#endif\r
- return IRQ_HANDLED;\r
-}\r
-\r
-\r
-#if defined(CONFIG_PM)\r
-static int rk3188_lcdc_suspend(struct platform_device *pdev,\r
- pm_message_t state)\r
-{\r
- return 0;\r
-}\r
-\r
-static int rk3188_lcdc_resume(struct platform_device *pdev)\r
-{\r
- return 0;\r
-}\r
-#else\r
-#define rk3188_lcdc_suspend NULL\r
-#define rk3188_lcdc_resume NULL\r
-#endif\r
-static int __devinit rk3188_lcdc_probe(struct platform_device *pdev)\r
-{\r
- struct rk3188_lcdc_device *lcdc_dev = NULL;\r
- struct device *dev = &pdev->dev;\r
- rk_screen *screen;\r
- struct rk29fb_info *screen_ctr_info;\r
- struct resource *res = NULL;\r
- struct resource *mem = NULL;\r
- int ret = 0;\r
- \r
- lcdc_dev = devm_kzalloc(dev,sizeof(struct rk3188_lcdc_device), GFP_KERNEL);\r
- if(!lcdc_dev)\r
- {\r
- dev_err(&pdev->dev, ">>rk3188 lcdc device kmalloc fail!");\r
- return -ENOMEM;\r
- }\r
- platform_set_drvdata(pdev, lcdc_dev);\r
- lcdc_dev->id = pdev->id;\r
- screen_ctr_info = (struct rk29fb_info * )pdev->dev.platform_data;\r
- if(!screen_ctr_info)\r
- {\r
- dev_err(dev, "no platform data specified for screen control info!\n");\r
- ret = -EINVAL;\r
- goto err0;\r
- }\r
- screen = kzalloc(sizeof(rk_screen), GFP_KERNEL);\r
- if(!screen)\r
- {\r
- dev_err(&pdev->dev, "rk screen kmalloc fail!");\r
- ret = -ENOMEM;\r
- goto err0;\r
- }\r
- \r
- res = platform_get_resource(pdev, IORESOURCE_MEM,0);\r
- if (res == NULL)\r
- {\r
- dev_err(&pdev->dev, "failed to get register resource for lcdc%d \n",lcdc_dev->id);\r
- ret = -ENOENT;\r
- goto err1;\r
- }\r
- \r
- lcdc_dev->reg_phy_base = res->start;\r
- lcdc_dev->len = resource_size(res);\r
- mem = request_mem_region(lcdc_dev->reg_phy_base,lcdc_dev->len, pdev->name);\r
- if (!mem)\r
- {\r
- dev_err(&pdev->dev, "failed to request mem region for lcdc%d\n",lcdc_dev->id);\r
- ret = -ENOENT;\r
- goto err1;\r
- }\r
- lcdc_dev->regs = ioremap(lcdc_dev->reg_phy_base,lcdc_dev->len);\r
- if (!lcdc_dev->regs)\r
- {\r
- dev_err(&pdev->dev, "cannot map register for lcdc%d\n",lcdc_dev->id);\r
- ret = -ENXIO;\r
- goto err2;\r
- }\r
- \r
- lcdc_dev->regsbak = kzalloc(lcdc_dev->len,GFP_KERNEL);\r
- if(!lcdc_dev->regsbak)\r
- {\r
- dev_err(&pdev->dev, "failed to map memory for reg backup!\n");\r
- ret = -ENOMEM;\r
- goto err3;\r
- }\r
- lcdc_dev->dsp_lut_addr_base = (lcdc_dev->regs + DSP_LUT_ADDR);\r
- printk("lcdc%d:reg_phy_base = 0x%08x,reg_vir_base:0x%p\n",pdev->id,lcdc_dev->reg_phy_base, lcdc_dev->regs);\r
- lcdc_dev->driver.dev = dev;\r
- lcdc_dev->driver.screen0 = screen;\r
- lcdc_dev->driver.cur_screen = screen;\r
- lcdc_dev->driver.screen_ctr_info = screen_ctr_info;\r
- \r
- spin_lock_init(&lcdc_dev->reg_lock);\r
- \r
- lcdc_dev->irq = platform_get_irq(pdev, 0);\r
- if(lcdc_dev->irq < 0)\r
- {\r
- dev_err(&pdev->dev, "cannot find IRQ for lcdc%d\n",lcdc_dev->id);\r
- goto err3;\r
- }\r
- ret = devm_request_irq(dev,lcdc_dev->irq, rk3188_lcdc_isr, IRQF_DISABLED,dev_name(dev),lcdc_dev);\r
- if (ret)\r
- {\r
- dev_err(&pdev->dev, "cannot requeset irq %d - err %d\n", lcdc_dev->irq, ret);\r
- ret = -EBUSY;\r
- goto err3;\r
- }\r
- ret = rk_fb_register(&(lcdc_dev->driver),&lcdc_driver,lcdc_dev->id);\r
- if(ret < 0)\r
- {\r
- dev_err(dev,"register fb for lcdc%d failed!\n",lcdc_dev->id);\r
- goto err4;\r
- }\r
- printk("rk3188 lcdc%d probe ok!\n",lcdc_dev->id);\r
- \r
- return 0;\r
-\r
-err4:\r
- free_irq(lcdc_dev->irq,lcdc_dev);\r
-err3:\r
- iounmap(lcdc_dev->regs);\r
-err2:\r
- release_mem_region(lcdc_dev->reg_phy_base,lcdc_dev->len);\r
-err1:\r
- kfree(screen);\r
-err0:\r
- platform_set_drvdata(pdev, NULL);\r
- kfree(lcdc_dev);\r
- \r
- return ret;\r
-}\r
-\r
-static int __devexit rk3188_lcdc_remove(struct platform_device *pdev)\r
-{\r
- return 0;\r
-}\r
-\r
-static void rk3188_lcdc_shutdown(struct platform_device *pdev)\r
-{\r
- \r
-}\r
-static struct platform_driver rk3188_lcdc_driver = {\r
- .probe = rk3188_lcdc_probe,\r
- .remove = __devexit_p(rk3188_lcdc_remove),\r
- .driver = {\r
- .name = "rk3188-lcdc",\r
- .owner = THIS_MODULE,\r
- },\r
- .suspend = rk3188_lcdc_suspend,\r
- .resume = rk3188_lcdc_resume,\r
- .shutdown = rk3188_lcdc_shutdown,\r
-};\r
-static int __init rk3188_lcdc_module_init(void)\r
-{\r
- return platform_driver_register(&rk3188_lcdc_driver);\r
-}\r
-\r
-static void __exit rk3188_lcdc_module_exit(void)\r
-{\r
- platform_driver_unregister(&rk3188_lcdc_driver);\r
-}\r
-fs_initcall(rk3188_lcdc_module_init);\r
-module_exit(rk3188_lcdc_module_exit);\r
+/*
+ * drivers/video/rockchip/lcdc/rk3188_lcdc.c
+ *
+ * Copyright (C) 2013 ROCKCHIP, Inc.
+ *Author:yxj<yxj@rock-chips.com>
+ *This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/string.h>
+#include <linux/mm.h>
+#include <linux/slab.h>
+#include <linux/device.h>
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/earlysuspend.h>
+#include <asm/div64.h>
+#include <asm/uaccess.h>
+#include "rk3188_lcdc.h"
+
+
+
+static int dbg_thresd = 0;
+module_param(dbg_thresd, int, S_IRUGO|S_IWUSR);
+#define DBG(level,x...) do { \
+ if(unlikely(dbg_thresd >= level)) \
+ printk(KERN_INFO x);} while (0)
+
+//#define WAIT_FOR_SYNC 1
+static int rk3188_lcdc_clk_enable(struct rk3188_lcdc_device *lcdc_dev)
+{
+
+ clk_enable(lcdc_dev->pd);
+ clk_enable(lcdc_dev->hclk);
+ clk_enable(lcdc_dev->dclk);
+ clk_enable(lcdc_dev->aclk);
+
+ spin_lock(&lcdc_dev->reg_lock);
+ lcdc_dev->clk_on = 1;
+ spin_unlock(&lcdc_dev->reg_lock);
+ printk("rk3188 lcdc%d clk enable...\n",lcdc_dev->id);
+
+ return 0;
+}
+
+static int rk3188_lcdc_clk_disable(struct rk3188_lcdc_device *lcdc_dev)
+{
+ spin_lock(&lcdc_dev->reg_lock);
+ lcdc_dev->clk_on = 0;
+ spin_unlock(&lcdc_dev->reg_lock);
+
+ clk_disable(lcdc_dev->dclk);
+ clk_disable(lcdc_dev->hclk);
+ clk_disable(lcdc_dev->aclk);
+ clk_disable(lcdc_dev->pd);
+ printk("rk3188 lcdc%d clk disable...\n",lcdc_dev->id);
+
+ return 0;
+}
+
+static int rk3188_lcdc_reg_resume(struct rk3188_lcdc_device *lcdc_dev)
+{
+ memcpy((u8*)lcdc_dev->regs, (u8*)lcdc_dev->regsbak, 0x84);
+ return 0;
+}
+
+
+//enable layer,open:1,enable;0 disable
+static int win0_open(struct rk3188_lcdc_device *lcdc_dev,bool open)
+{
+ spin_lock(&lcdc_dev->reg_lock);
+ if(likely(lcdc_dev->clk_on))
+ {
+ if(open)
+ {
+ if(!lcdc_dev->atv_layer_cnt)
+ {
+ printk(KERN_INFO "lcdc%d wakeup from standby!\n",lcdc_dev->id);
+ lcdc_msk_reg(lcdc_dev, SYS_CTRL,m_LCDC_STANDBY,v_LCDC_STANDBY(0));
+ }
+ lcdc_dev->atv_layer_cnt++;
+ }
+ else if((lcdc_dev->atv_layer_cnt > 0) && (!open))
+ {
+ lcdc_dev->atv_layer_cnt--;
+ }
+ lcdc_dev->driver.layer_par[0]->state = open;
+
+ lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_WIN0_EN, v_WIN0_EN(open));
+ if(!lcdc_dev->atv_layer_cnt) //if no layer used,disable lcdc
+ {
+ printk(KERN_INFO "no layer of lcdc%d is used,go to standby!\n",lcdc_dev->id);
+ lcdc_msk_reg(lcdc_dev, SYS_CTRL,m_LCDC_STANDBY,v_LCDC_STANDBY(1));
+ }
+ lcdc_cfg_done(lcdc_dev);
+ }
+ spin_unlock(&lcdc_dev->reg_lock);
+
+
+ return 0;
+}
+
+static int win1_open(struct rk3188_lcdc_device *lcdc_dev,bool open)
+{
+ spin_lock(&lcdc_dev->reg_lock);
+ if(likely(lcdc_dev->clk_on))
+ {
+ if(open)
+ {
+ if(!lcdc_dev->atv_layer_cnt)
+ {
+ printk(KERN_INFO "lcdc%d wakeup from standby!\n",lcdc_dev->id);
+ lcdc_msk_reg(lcdc_dev, SYS_CTRL,m_LCDC_STANDBY,v_LCDC_STANDBY(0));
+ }
+ lcdc_dev->atv_layer_cnt++;
+ }
+ else if((lcdc_dev->atv_layer_cnt > 0) && (!open))
+ {
+ lcdc_dev->atv_layer_cnt--;
+ }
+ lcdc_dev->driver.layer_par[1]->state = open;
+
+ lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_WIN1_EN, v_WIN1_EN(open));
+ if(!lcdc_dev->atv_layer_cnt) //if no layer used,disable lcdc
+ {
+ printk(KERN_INFO "no layer of lcdc%d is used,go to standby!\n",lcdc_dev->id);
+ lcdc_msk_reg(lcdc_dev, SYS_CTRL,m_LCDC_STANDBY,v_LCDC_STANDBY(1));
+ }
+ lcdc_cfg_done(lcdc_dev);
+ }
+ spin_unlock(&lcdc_dev->reg_lock);
+
+ return 0;
+}
+
+static int rk3188_lcdc_open(struct rk_lcdc_device_driver *dev_drv,int layer_id,bool open)
+{
+ int i=0;
+ int __iomem *c;
+ int v;
+ struct rk3188_lcdc_device *lcdc_dev =
+ container_of(dev_drv,struct rk3188_lcdc_device,driver);
+
+ if((open) && (!lcdc_dev->atv_layer_cnt)) //enable clk,when first layer open
+ {
+ rk3188_lcdc_clk_enable(lcdc_dev);
+ rk3188_lcdc_reg_resume(lcdc_dev); //resume reg
+ spin_lock(&lcdc_dev->reg_lock);
+ if(dev_drv->cur_screen->dsp_lut) //resume dsp lut
+ {
+ lcdc_msk_reg(lcdc_dev,SYS_CTRL,m_DSP_LUT_EN,v_DSP_LUT_EN(0));
+ lcdc_cfg_done(lcdc_dev);
+ mdelay(25); //wait for dsp lut disabled
+ for(i=0;i<256;i++)
+ {
+ v = dev_drv->cur_screen->dsp_lut[i];
+ c = lcdc_dev->dsp_lut_addr_base+i;
+ writel_relaxed(v,c);
+
+ }
+ lcdc_msk_reg(lcdc_dev,SYS_CTRL,m_DSP_LUT_EN,v_DSP_LUT_EN(1)); //enable dsp lut
+ }
+ spin_unlock(&lcdc_dev->reg_lock);
+ }
+
+ if(layer_id == 0)
+ {
+ win0_open(lcdc_dev,open);
+ }
+ else if(layer_id == 1)
+ {
+ win1_open(lcdc_dev,open);
+ }
+ else
+ {
+ printk("invalid win number:%d\n",layer_id);
+ }
+
+ if((!open) && (!lcdc_dev->atv_layer_cnt)) //when all layer closed,disable clk
+ {
+ rk3188_lcdc_clk_disable(lcdc_dev);
+ }
+
+ printk(KERN_INFO "lcdc%d win%d %s,atv layer:%d\n",
+ lcdc_dev->id,layer_id,open?"open":"closed",
+ lcdc_dev->atv_layer_cnt);
+ return 0;
+}
+
+static int rk3188_lcdc_init(struct rk_lcdc_device_driver *dev_drv)
+{
+ int i = 0;
+ int __iomem *c;
+ int v;
+ struct rk3188_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk3188_lcdc_device,driver);
+ if(lcdc_dev->id == 0) //lcdc0
+ {
+ lcdc_dev->pd = clk_get(NULL,"pd_lcdc0");
+ lcdc_dev->hclk = clk_get(NULL,"hclk_lcdc0");
+ lcdc_dev->aclk = clk_get(NULL,"aclk_lcdc0");
+ lcdc_dev->dclk = clk_get(NULL,"dclk_lcdc0");
+ }
+ else if(lcdc_dev->id == 1)
+ {
+ lcdc_dev->pd = clk_get(NULL,"pd_lcdc1");
+ lcdc_dev->hclk = clk_get(NULL,"hclk_lcdc1");
+ lcdc_dev->aclk = clk_get(NULL,"aclk_lcdc1");
+ lcdc_dev->dclk = clk_get(NULL,"dclk_lcdc1");
+ }
+ else
+ {
+ printk(KERN_ERR "invalid lcdc device!\n");
+ return -EINVAL;
+ }
+ if (IS_ERR(lcdc_dev->pd) || (IS_ERR(lcdc_dev->aclk)) ||(IS_ERR(lcdc_dev->dclk)) || (IS_ERR(lcdc_dev->hclk)))
+ {
+ printk(KERN_ERR "failed to get lcdc%d clk source\n",lcdc_dev->id);
+ }
+
+ rk3188_lcdc_clk_enable(lcdc_dev);
+
+ lcdc_set_bit(lcdc_dev,SYS_CTRL,m_AUTO_GATING_EN);//eanble axi-clk auto gating for low power
+ if(dev_drv->cur_screen->dsp_lut)
+ {
+ lcdc_msk_reg(lcdc_dev,SYS_CTRL,m_DSP_LUT_EN,v_DSP_LUT_EN(0));
+ lcdc_cfg_done(lcdc_dev);
+ msleep(25);
+ for(i=0;i<256;i++)
+ {
+ v = dev_drv->cur_screen->dsp_lut[i];
+ c = lcdc_dev->dsp_lut_addr_base+i;
+ writel_relaxed(v,c);
+
+ }
+ lcdc_msk_reg(lcdc_dev,SYS_CTRL,m_DSP_LUT_EN,v_DSP_LUT_EN(1));
+ }
+
+ lcdc_cfg_done(lcdc_dev); // write any value to REG_CFG_DONE let config become effective
+
+ rk3188_lcdc_clk_disable(lcdc_dev);
+
+ return 0;
+}
+
+
+//set lcdc according the screen info
+static int rk3188_load_screen(struct rk_lcdc_device_driver *dev_drv, bool initscreen)
+{
+ int ret = -EINVAL;
+ int fps;
+ u16 face = 0;
+ struct rk3188_lcdc_device *lcdc_dev =
+ container_of(dev_drv,struct rk3188_lcdc_device,driver);
+ rk_screen *screen = dev_drv->cur_screen;
+ u16 right_margin = screen->right_margin;
+ u16 left_margin = screen->left_margin;
+ u16 lower_margin = screen->lower_margin;
+ u16 upper_margin = screen->upper_margin;
+ u16 x_res = screen->x_res;
+ u16 y_res = screen->y_res;
+
+
+ spin_lock(&lcdc_dev->reg_lock);
+ if(likely(lcdc_dev->clk_on))
+ {
+ if(screen->type==SCREEN_MCU)
+ {
+ printk("MUC¡¡screen not supported now!\n");
+ return -EINVAL;
+ }
+
+ switch (screen->face)
+ {
+ case OUT_P565:
+ face = OUT_P565; //dither down to rgb565
+ lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE, v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(0));
+ break;
+ case OUT_P666:
+ face = OUT_P666; //dither down to rgb666
+ lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE, v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(1));
+ break;
+ case OUT_D888_P565:
+ face = OUT_P888;
+ lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE, v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(0));
+ break;
+ case OUT_D888_P666:
+ face = OUT_P888;
+ lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE, v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(1));
+ break;
+ case OUT_P888:
+ face = OUT_P888;
+ break;
+ default:
+ printk("unsupported display output interface!\n");
+ break;
+ }
+
+ //use default overlay,set vsyn hsync den dclk polarity
+ lcdc_msk_reg(lcdc_dev, DSP_CTRL0,m_DSP_OUT_FORMAT | m_HSYNC_POL | m_VSYNC_POL |
+ m_DEN_POL |m_DCLK_POL,v_DSP_OUT_FORMAT(face) | v_HSYNC_POL(screen->pin_hsync) |
+ v_VSYNC_POL(screen->pin_vsync) | v_DEN_POL(screen->pin_den) | v_DCLK_POL(screen->pin_dclk));
+
+
+ //set background color to black,set swap according to the screen panel,disable blank mode
+ lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_BG_COLOR| m_DSP_BG_SWAP | m_DSP_RB_SWAP |
+ m_DSP_RG_SWAP | m_DSP_DELTA_SWAP | m_DSP_DUMMY_SWAP | m_BLANK_EN,
+ v_BG_COLOR(0x000000) | v_DSP_BG_SWAP(screen->swap_gb) |
+ v_DSP_RB_SWAP(screen->swap_rb) | v_DSP_RG_SWAP(screen->swap_rg) |
+ v_DSP_DELTA_SWAP(screen->swap_delta) | v_DSP_DUMMY_SWAP(screen->swap_dumy) |
+ v_BLANK_EN(0) | v_BLACK_EN(0));
+ lcdc_writel(lcdc_dev,DSP_HTOTAL_HS_END,v_HSYNC(screen->hsync_len) |
+ v_HORPRD(screen->hsync_len + left_margin + x_res + right_margin));
+ lcdc_writel(lcdc_dev,DSP_HACT_ST_END,v_HAEP(screen->hsync_len + left_margin + x_res) |
+ v_HASP(screen->hsync_len + left_margin));
+
+ lcdc_writel(lcdc_dev,DSP_VTOTAL_VS_END, v_VSYNC(screen->vsync_len) |
+ v_VERPRD(screen->vsync_len + upper_margin + y_res + lower_margin));
+ lcdc_writel(lcdc_dev,DSP_VACT_ST_END,v_VAEP(screen->vsync_len + upper_margin+y_res)|
+ v_VASP(screen->vsync_len + screen->upper_margin));
+ }
+ spin_unlock(&lcdc_dev->reg_lock);
+
+ ret = clk_set_rate(lcdc_dev->dclk, screen->pixclock);
+ if(ret)
+ {
+ dev_err(dev_drv->dev,"set lcdc%d dclk failed\n",lcdc_dev->id);
+ }
+ lcdc_dev->driver.pixclock = lcdc_dev->pixclock = div_u64(1000000000000llu, clk_get_rate(lcdc_dev->dclk));
+
+ fps = rk_fb_calc_fps(screen,lcdc_dev->pixclock);
+ screen->ft = 1000/fps;
+ printk("%s: dclk:%lu>>fps:%d ",lcdc_dev->driver.name,clk_get_rate(lcdc_dev->dclk),fps);
+
+ if(screen->init)
+ {
+ screen->init();
+ }
+
+ dev_info(dev_drv->dev,"%s for lcdc%d ok!\n",__func__,lcdc_dev->id);
+ return 0;
+}
+
+
+static int win0_set_par(struct rk3188_lcdc_device *lcdc_dev,rk_screen *screen,
+ struct layer_par *par )
+{
+ u32 xact, yact, xvir, yvir, xpos, ypos;
+ u32 ScaleYrgbX = 0x1000;
+ u32 ScaleYrgbY = 0x1000;
+ u32 ScaleCbrX = 0x1000;
+ u32 ScaleCbrY = 0x1000;
+
+ xact = par->xact; //active (origin) picture window width/height
+ yact = par->yact;
+ xvir = par->xvir; // virtual resolution
+ yvir = par->yvir;
+ xpos = par->xpos+screen->left_margin + screen->hsync_len;
+ ypos = par->ypos+screen->upper_margin + screen->vsync_len;
+
+
+ ScaleYrgbX = CalScale(xact, par->xsize); //both RGB and yuv need this two factor
+ ScaleYrgbY = CalScale(yact, par->ysize);
+ switch (par->format)
+ {
+ case YUV422:// yuv422
+ ScaleCbrX = CalScale((xact/2), par->xsize);
+ ScaleCbrY = CalScale(yact, par->ysize);
+ break;
+ case YUV420: // yuv420
+ ScaleCbrX = CalScale(xact/2, par->xsize);
+ ScaleCbrY = CalScale(yact/2, par->ysize);
+ break;
+ case YUV444:// yuv444
+ ScaleCbrX = CalScale(xact, par->xsize);
+ ScaleCbrY = CalScale(yact, par->ysize);
+ break;
+ default:
+ break;
+ }
+
+ DBG(1,"%s for lcdc%d>>format:%d>>>xact:%d>>yact:%d>>xsize:%d>>ysize:%d>>xvir:%d>>yvir:%d>>xpos:%d>>ypos:%d>>\n",
+ __func__,lcdc_dev->id,par->format,xact,yact,par->xsize,par->ysize,xvir,yvir,xpos,ypos);
+
+ spin_lock(&lcdc_dev->reg_lock);
+ if(likely(lcdc_dev->clk_on))
+ {
+ lcdc_writel(lcdc_dev,WIN0_SCL_FACTOR_YRGB,v_X_SCL_FACTOR(ScaleYrgbX) | v_Y_SCL_FACTOR(ScaleYrgbY));
+ lcdc_writel(lcdc_dev,WIN0_SCL_FACTOR_CBR,v_X_SCL_FACTOR(ScaleCbrX) | v_Y_SCL_FACTOR(ScaleCbrY));
+ lcdc_msk_reg(lcdc_dev,SYS_CTRL,m_WIN0_FORMAT,v_WIN0_FORMAT(par->format)); //(inf->video_mode==0)
+ lcdc_writel(lcdc_dev,WIN0_ACT_INFO,v_ACT_WIDTH(xact) | v_ACT_HEIGHT(yact));
+ lcdc_writel(lcdc_dev,WIN0_DSP_ST,v_DSP_STX(xpos) | v_DSP_STY(ypos));
+ lcdc_writel(lcdc_dev,WIN0_DSP_INFO,v_DSP_WIDTH(par->xsize) | v_DSP_HEIGHT(par->ysize));
+ lcdc_msk_reg(lcdc_dev,WIN0_COLOR_KEY,m_COLOR_KEY_EN,v_COLOR_KEY_EN(0));
+
+ switch(par->format)
+ {
+ case ARGB888:
+ lcdc_msk_reg(lcdc_dev, WIN_VIR,m_WIN0_VIR,v_ARGB888_VIRWIDTH(xvir));
+ //lcdc_msk_reg(lcdc_dev,SYS_CTRL1,m_W0_RGB_RB_SWAP,v_W0_RGB_RB_SWAP(1));
+ break;
+ case RGB888: //rgb888
+ lcdc_msk_reg(lcdc_dev, WIN_VIR,m_WIN0_VIR,v_RGB888_VIRWIDTH(xvir));
+ //lcdc_msk_reg(lcdc_dev,SYS_CTRL1,m_W0_RGB_RB_SWAP,v_W0_RGB_RB_SWAP(1));
+ break;
+ case RGB565: //rgb565
+ lcdc_msk_reg(lcdc_dev, WIN_VIR,m_WIN0_VIR,v_RGB565_VIRWIDTH(xvir));
+ break;
+ case YUV422:
+ case YUV420:
+ case YUV444:
+ lcdc_msk_reg(lcdc_dev, WIN_VIR,m_WIN0_VIR,v_YUV_VIRWIDTH(xvir));
+ break;
+ default:
+ dev_err(lcdc_dev->driver.dev,"un supported format!\n");
+ break;
+ }
+
+ }
+ spin_unlock(&lcdc_dev->reg_lock);
+
+ return 0;
+
+}
+
+static int win1_set_par(struct rk3188_lcdc_device *lcdc_dev,rk_screen *screen,
+ struct layer_par *par )
+{
+ u32 xact, yact, xvir, yvir, xpos, ypos;
+
+ xact = par->xact;
+ yact = par->yact;
+ xvir = par->xvir;
+ yvir = par->yvir;
+ xpos = par->xpos+screen->left_margin + screen->hsync_len;
+ ypos = par->ypos+screen->upper_margin + screen->vsync_len;
+
+
+ DBG(1,"%s for lcdc%d>>format:%d>>>xact:%d>>yact:%d>>xsize:%d>>ysize:%d>>xvir:%d>>yvir:%d>>xpos:%d>>ypos:%d>>\n",
+ __func__,lcdc_dev->id,par->format,xact,yact,par->xsize,par->ysize,xvir,yvir,xpos,ypos);
+
+
+ spin_lock(&lcdc_dev->reg_lock);
+ if(likely(lcdc_dev->clk_on))
+ {
+ lcdc_msk_reg(lcdc_dev,SYS_CTRL,m_WIN1_FORMAT, v_WIN1_FORMAT(par->format));
+ lcdc_writel(lcdc_dev, WIN1_DSP_INFO,v_DSP_WIDTH(par->xsize) | v_DSP_HEIGHT(par->ysize));
+ lcdc_writel(lcdc_dev, WIN1_DSP_ST,v_DSP_STX(xpos) | v_DSP_STY(ypos));
+ // disable win1 color key and set the color to black(rgb=0)
+ lcdc_msk_reg(lcdc_dev, WIN1_COLOR_KEY,m_COLOR_KEY_EN,v_COLOR_KEY_EN(0));
+ switch(par->format)
+ {
+ case ARGB888:
+ lcdc_msk_reg(lcdc_dev, WIN_VIR,m_WIN1_VIR,v_WIN1_ARGB888_VIRWIDTH(xvir));
+ //lcdc_msk_reg(lcdc_dev,SYS_CTRL1,m_W1_RGB_RB_SWAP,v_W1_RGB_RB_SWAP(1));
+ break;
+ case RGB888: //rgb888
+ lcdc_msk_reg(lcdc_dev, WIN_VIR,m_WIN1_VIR,v_WIN1_RGB888_VIRWIDTH(xvir));
+ // lcdc_msk_reg(lcdc_dev,SYS_CTRL1,m_W1_RGB_RB_SWAP,v_W1_RGB_RB_SWAP(1));
+ break;
+ case RGB565: //rgb565
+ lcdc_msk_reg(lcdc_dev, WIN_VIR,m_WIN1_VIR,v_WIN1_RGB565_VIRWIDTH(xvir));
+ break;
+ default:
+ dev_err(lcdc_dev->driver.dev,"un supported format!\n");
+ break;
+ }
+
+ }
+ spin_unlock(&lcdc_dev->reg_lock);
+
+ return 0;
+}
+
+
+static int rk3188_lcdc_set_par(struct rk_lcdc_device_driver *dev_drv,int layer_id)
+{
+ struct rk3188_lcdc_device *lcdc_dev =
+ container_of(dev_drv,struct rk3188_lcdc_device,driver);
+ struct layer_par *par = NULL;
+ rk_screen *screen = dev_drv->cur_screen;
+
+ if(!screen)
+ {
+ dev_err(dev_drv->dev,"screen is null!\n");
+ return -ENOENT;
+ }
+ if(layer_id==0)
+ {
+ par = dev_drv->layer_par[0];
+ win0_set_par(lcdc_dev,screen,par);
+ }
+ else if(layer_id==1)
+ {
+ par = dev_drv->layer_par[1];
+ win1_set_par(lcdc_dev,screen,par);
+ }
+ else
+ {
+ dev_err(dev_drv->dev,"unsupported win number:%d\n",layer_id);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int win0_display(struct rk3188_lcdc_device *lcdc_dev,struct layer_par *par )
+{
+ u32 y_addr;
+ u32 uv_addr;
+ y_addr = par->smem_start + par->y_offset;
+ uv_addr = par->cbr_start + par->c_offset;
+ DBG(2,KERN_INFO "lcdc%d>>%s:y_addr:0x%x>>uv_addr:0x%x\n",lcdc_dev->id,__func__,y_addr,uv_addr);
+
+ spin_lock(&lcdc_dev->reg_lock);
+ if(likely(lcdc_dev->clk_on))
+ {
+ lcdc_writel(lcdc_dev, WIN0_YRGB_MST0, y_addr);
+ lcdc_writel(lcdc_dev, WIN0_CBR_MST0, uv_addr);
+ lcdc_cfg_done(lcdc_dev);
+ }
+ spin_unlock(&lcdc_dev->reg_lock);
+
+ return 0;
+
+}
+
+static int win1_display(struct rk3188_lcdc_device *lcdc_dev,struct layer_par *par )
+{
+ u32 y_addr;
+ u32 uv_addr;
+ y_addr = par->smem_start + par->y_offset;
+ uv_addr = par->cbr_start + par->c_offset;
+ DBG(2,KERN_INFO "lcdc%d>>%s>>y_addr:0x%x>>uv_addr:0x%x\n",lcdc_dev->id,__func__,y_addr,uv_addr);
+
+ spin_lock(&lcdc_dev->reg_lock);
+ if(likely(lcdc_dev->clk_on))
+ {
+ lcdc_writel(lcdc_dev,WIN1_MST,y_addr);
+ lcdc_cfg_done(lcdc_dev);
+ }
+ spin_unlock(&lcdc_dev->reg_lock);
+
+ return 0;
+}
+
+static int rk3188_lcdc_pan_display(struct rk_lcdc_device_driver * dev_drv,int layer_id)
+{
+ struct rk3188_lcdc_device *lcdc_dev =
+ container_of(dev_drv,struct rk3188_lcdc_device,driver);
+ struct layer_par *par = NULL;
+ rk_screen *screen = dev_drv->cur_screen;
+ unsigned long flags;
+ int timeout;
+
+ if(!screen)
+ {
+ dev_err(dev_drv->dev,"screen is null!\n");
+ return -ENOENT;
+ }
+ if(layer_id==0)
+ {
+ par = dev_drv->layer_par[0];
+ win0_display(lcdc_dev,par);
+ }
+ else if(layer_id==1)
+ {
+ par = dev_drv->layer_par[1];
+ win1_display(lcdc_dev,par);
+ }
+ else
+ {
+ dev_err(dev_drv->dev,"invalid win number:%d!\n",layer_id);
+ return -EINVAL;
+ }
+ if((dev_drv->first_frame)) //this is the first frame of the system ,enable frame start interrupt
+ {
+ dev_drv->first_frame = 0;
+ lcdc_msk_reg(lcdc_dev,INT_STATUS,m_FS_INT_CLEAR |m_FS_INT_EN ,
+ v_FS_INT_CLEAR(1) | v_FS_INT_EN(1));
+ lcdc_cfg_done(lcdc_dev); // write any value to REG_CFG_DONE let config become effective
+
+ }
+
+#if defined(WAIT_FOR_SYNC)
+ spin_lock_irqsave(&dev_drv->cpl_lock,flags);
+ init_completion(&dev_drv->frame_done);
+ spin_unlock_irqrestore(&dev_drv->cpl_lock,flags);
+ timeout = wait_for_completion_timeout(&dev_drv->frame_done,msecs_to_jiffies(dev_drv->cur_screen->ft+5));
+ if(!timeout&&(!dev_drv->frame_done.done))
+ {
+ printk(KERN_ERR "wait for new frame start time out!\n");
+ return -ETIMEDOUT;
+ }
+#endif
+ return 0;
+}
+
+static int rk3188_lcdc_blank(struct rk_lcdc_device_driver *dev_drv,
+ int layer_id,int blank_mode)
+{
+ struct rk3188_lcdc_device * lcdc_dev =
+ container_of(dev_drv,struct rk3188_lcdc_device,driver);
+
+ spin_lock(&lcdc_dev->reg_lock);
+ if(likely(lcdc_dev->clk_on))
+ {
+ switch(blank_mode)
+ {
+ case FB_BLANK_UNBLANK:
+ lcdc_msk_reg(lcdc_dev,DSP_CTRL1,m_BLANK_EN ,v_BLANK_EN(0));
+ break;
+ case FB_BLANK_NORMAL:
+ lcdc_msk_reg(lcdc_dev,DSP_CTRL1,m_BLANK_EN ,v_BLANK_EN(1));
+ break;
+ default:
+ lcdc_msk_reg(lcdc_dev,DSP_CTRL1,m_BLANK_EN ,v_BLANK_EN(1));
+ break;
+ }
+ lcdc_cfg_done(lcdc_dev);
+ dev_info(dev_drv->dev,"blank mode:%d\n",blank_mode);
+ }
+ spin_unlock(&lcdc_dev->reg_lock);
+
+ return 0;
+}
+
+
+static int rk3188_lcdc_ioctl(struct rk_lcdc_device_driver *dev_drv, unsigned int cmd,unsigned long arg,int layer_id)
+{
+ return 0;
+}
+
+static int rk3188_lcdc_early_suspend(struct rk_lcdc_device_driver *dev_drv)
+{
+
+ struct rk3188_lcdc_device *lcdc_dev =
+ container_of(dev_drv,struct rk3188_lcdc_device,driver);
+
+ spin_lock(&lcdc_dev->reg_lock);
+ if(likely(lcdc_dev->clk_on))
+ {
+ lcdc_msk_reg(lcdc_dev,INT_STATUS,m_FS_INT_CLEAR,v_FS_INT_CLEAR(1));
+ lcdc_msk_reg(lcdc_dev,SYS_CTRL,m_LCDC_STANDBY,v_LCDC_STANDBY(1));
+ lcdc_cfg_done(lcdc_dev);
+ spin_unlock(&lcdc_dev->reg_lock);
+ }
+ else //clk already disabled
+ {
+ spin_unlock(&lcdc_dev->reg_lock);
+ return 0;
+ }
+
+ rk3188_lcdc_clk_disable(lcdc_dev);
+ return 0;
+}
+
+static int rk3188_lcdc_early_resume(struct rk_lcdc_device_driver *dev_drv)
+{
+ struct rk3188_lcdc_device *lcdc_dev =
+ container_of(dev_drv,struct rk3188_lcdc_device,driver);
+ int i=0;
+ int __iomem *c;
+ int v;
+ if(!lcdc_dev->clk_on)
+ {
+ rk3188_lcdc_clk_enable(lcdc_dev);
+ }
+ rk3188_lcdc_reg_resume(lcdc_dev); //resume reg
+
+ spin_lock(&lcdc_dev->reg_lock);
+ if(dev_drv->cur_screen->dsp_lut) //resume dsp lut
+ {
+ lcdc_msk_reg(lcdc_dev,SYS_CTRL,m_DSP_LUT_EN,v_DSP_LUT_EN(0));
+ lcdc_cfg_done(lcdc_dev);
+ mdelay(25);
+ for(i=0;i<256;i++)
+ {
+ v = dev_drv->cur_screen->dsp_lut[i];
+ c = lcdc_dev->dsp_lut_addr_base+i;
+ writel_relaxed(v,c);
+ }
+ lcdc_msk_reg(lcdc_dev,SYS_CTRL,m_DSP_LUT_EN,v_DSP_LUT_EN(1));
+ }
+
+ if(lcdc_dev->atv_layer_cnt)
+ {
+ lcdc_msk_reg(lcdc_dev, SYS_CTRL,m_LCDC_STANDBY,v_LCDC_STANDBY(0));
+ lcdc_cfg_done(lcdc_dev);
+ }
+ spin_unlock(&lcdc_dev->reg_lock);
+
+ if(!lcdc_dev->atv_layer_cnt)
+ rk3188_lcdc_clk_disable(lcdc_dev);
+
+ return 0;
+}
+
+static int rk3188_lcdc_get_layer_state(struct rk_lcdc_device_driver *dev_drv,int layer_id)
+{
+ return 0;
+}
+
+static int rk3188_lcdc_ovl_mgr(struct rk_lcdc_device_driver *dev_drv,int swap,bool set)
+{
+ return 0;
+}
+
+
+static ssize_t dump_win0_disp_info(struct rk3188_lcdc_device *lcdc_dev,char *buf)
+{
+ char format[9] = "NULL";
+ u32 fmt_id = lcdc_readl(lcdc_dev,SYS_CTRL);
+ u32 xvir,act_info,dsp_info,dsp_st,factor;
+ u16 x_act,y_act,x_dsp,y_dsp,x_factor,y_factor;
+ u16 x_scale,y_scale;
+ switch((fmt_id&m_WIN0_FORMAT)>>3)
+ {
+ case 0:
+ strcpy(format,"ARGB888");
+ break;
+ case 1:
+ strcpy(format,"RGB888");
+ break;
+ case 2:
+ strcpy(format,"RGB565");
+ break;
+ case 4:
+ strcpy(format,"YCbCr420");
+ break;
+ case 5:
+ strcpy(format,"YCbCr422");
+ break;
+ case 6:
+ strcpy(format,"YCbCr444");
+ break;
+ default:
+ strcpy(format,"invalid\n");
+ break;
+ }
+
+ xvir = lcdc_readl(lcdc_dev,WIN_VIR)&0x1fff;
+ act_info = lcdc_readl(lcdc_dev,WIN0_ACT_INFO);
+ dsp_info = lcdc_readl(lcdc_dev,WIN0_DSP_INFO);
+ dsp_st = lcdc_readl(lcdc_dev,WIN0_DSP_ST);
+ factor = lcdc_readl(lcdc_dev,WIN0_SCL_FACTOR_YRGB);
+ x_act = (act_info&0x1fff) + 1;
+ y_act = ((act_info>>16)&0x1fff) + 1;
+ x_dsp = (dsp_info&0x7ff) + 1;
+ y_dsp = ((dsp_info>>16)&0x7ff) + 1;
+ x_factor = factor&0xffff;
+ y_factor = factor>>16;
+ x_scale = 4096*100/x_factor;
+ y_scale = 4096*100/y_factor;
+ return snprintf(buf,PAGE_SIZE,
+ "xvir:%d\n"
+ "xact:%d\n"
+ "yact:%d\n"
+ "xdsp:%d\n"
+ "ydsp:%d\n"
+ "x_st:%d\n"
+ "y_st:%d\n"
+ "x_scale:%d.%d\n"
+ "y_scale:%d.%d\n"
+ "format:%s\n",
+ xvir,
+ x_act,
+ y_act,
+ x_dsp,
+ y_dsp,
+ dsp_st&0xffff,
+ dsp_st>>16,
+ x_scale/100,
+ x_scale%100,
+ y_scale/100,
+ y_scale%100,
+ format);
+
+}
+
+
+static ssize_t dump_win1_disp_info(struct rk3188_lcdc_device *lcdc_dev,char *buf)
+{
+ char format[9] = "NULL";
+ u32 fmt_id = lcdc_readl(lcdc_dev,SYS_CTRL);
+ u32 xvir,dsp_info,dsp_st;
+ u16 x_dsp,y_dsp;
+
+ switch((fmt_id&m_WIN1_FORMAT)>>6)
+ {
+ case 0:
+ strcpy(format,"ARGB888");
+ break;
+ case 1:
+ strcpy(format,"RGB888");
+ break;
+ case 2:
+ strcpy(format,"RGB565");
+ break;
+ case 4:
+ strcpy(format,"8bpp");
+ break;
+ case 5:
+ strcpy(format,"4bpp");
+ break;
+ case 6:
+ strcpy(format,"2bpp");
+ break;
+ case 7:
+ strcpy(format,"1bpp");
+ break;
+ default:
+ strcpy(format,"inval\n");
+ break;
+ }
+
+ xvir = (lcdc_readl(lcdc_dev,WIN_VIR)>> 16)&0x1fff;
+ dsp_info = lcdc_readl(lcdc_dev,WIN1_DSP_INFO);
+ dsp_st = lcdc_readl(lcdc_dev,WIN1_DSP_ST);
+ x_dsp = (dsp_info&0x7ff) + 1;
+ y_dsp = ((dsp_info>>16)&0x7ff) + 1;
+
+ return snprintf(buf,PAGE_SIZE,
+ "xvir:%d\n"
+ "xdsp:%d\n"
+ "ydsp:%d\n"
+ "x_st:%d\n"
+ "y_st:%d\n"
+ "format:%s\n",
+ xvir,
+ x_dsp,
+ y_dsp,
+ dsp_st&0xffff,
+ dsp_st>>16,
+ format);
+}
+
+static ssize_t rk3188_lcdc_get_disp_info(struct rk_lcdc_device_driver *dev_drv,char *buf,int layer_id)
+{
+
+ struct rk3188_lcdc_device *lcdc_dev =
+ container_of(dev_drv,struct rk3188_lcdc_device,driver);
+ if(layer_id == 0)
+ {
+ return dump_win0_disp_info(lcdc_dev,buf);
+ }
+ else if(layer_id == 1)
+ {
+ return dump_win1_disp_info(lcdc_dev,buf);
+ }
+ else
+ {
+ dev_err(dev_drv->dev,"invalid win number:%d\n",layer_id);
+ }
+ return 0;
+}
+
+static int rk3188_lcdc_fps_mgr(struct rk_lcdc_device_driver *dev_drv,int fps,bool set)
+{
+ return 0;
+}
+
+
+static int rk3188_fb_layer_remap(struct rk_lcdc_device_driver *dev_drv,
+ enum fb_win_map_order order)
+{
+ mutex_lock(&dev_drv->fb_win_id_mutex);
+ if(order == FB_DEFAULT_ORDER )
+ {
+ order = FB0_WIN0_FB1_WIN1_FB2_WIN2;
+ }
+ dev_drv->fb2_win_id = order/100;
+ dev_drv->fb1_win_id = (order/10)%10;
+ dev_drv->fb0_win_id = order%10;
+ mutex_unlock(&dev_drv->fb_win_id_mutex);
+
+ printk("fb0:win%d\nfb1:win%d\nfb2:win%d\n",dev_drv->fb0_win_id,dev_drv->fb1_win_id,
+ dev_drv->fb2_win_id);
+
+ return 0;
+}
+
+static int rk3188_fb_get_layer(struct rk_lcdc_device_driver *dev_drv,const char *id)
+{
+ int layer_id = 0;
+ mutex_lock(&dev_drv->fb_win_id_mutex);
+ if(!strcmp(id,"fb0")||!strcmp(id,"fb2"))
+ {
+ layer_id = dev_drv->fb0_win_id;
+ }
+ else if(!strcmp(id,"fb1")||!strcmp(id,"fb3"))
+ {
+ layer_id = dev_drv->fb1_win_id;
+ }
+ mutex_unlock(&dev_drv->fb_win_id_mutex);
+
+ return layer_id;
+}
+
+static int rk3188_set_dsp_lut(struct rk_lcdc_device_driver *dev_drv,int *lut)
+{
+ int i=0;
+ int __iomem *c;
+ int v;
+ int ret = 0;
+
+ struct rk3188_lcdc_device *lcdc_dev =
+ container_of(dev_drv,struct rk3188_lcdc_device,driver);
+ lcdc_msk_reg(lcdc_dev,SYS_CTRL,m_DSP_LUT_EN,v_DSP_LUT_EN(0));
+ lcdc_cfg_done(lcdc_dev);
+ msleep(25);
+ if(dev_drv->cur_screen->dsp_lut)
+ {
+ for(i=0;i<256;i++)
+ {
+ v = dev_drv->cur_screen->dsp_lut[i] = lut[i];
+ c = lcdc_dev->dsp_lut_addr_base+i;
+ writel_relaxed(v,c);
+
+ }
+ }
+ else
+ {
+ dev_err(dev_drv->dev,"no buffer to backup lut data!\n");
+ ret = -1;
+ }
+ lcdc_msk_reg(lcdc_dev,SYS_CTRL,m_DSP_LUT_EN,v_DSP_LUT_EN(1));
+ lcdc_cfg_done(lcdc_dev);
+
+ return ret;
+}
+
+static struct layer_par lcdc_layer[] = {
+ [0] = {
+ .name = "win0",
+ .id = 0,
+ .support_3d = true,
+ },
+ [1] = {
+ .name = "win1",
+ .id = 1,
+ .support_3d = false,
+ },
+};
+
+static struct rk_lcdc_device_driver lcdc_driver = {
+ .name = "lcdc",
+ .def_layer_par = lcdc_layer,
+ .num_layer = ARRAY_SIZE(lcdc_layer),
+ .open = rk3188_lcdc_open,
+ .init_lcdc = rk3188_lcdc_init,
+ .load_screen = rk3188_load_screen,
+ .set_par = rk3188_lcdc_set_par,
+ .pan_display = rk3188_lcdc_pan_display,
+ .blank = rk3188_lcdc_blank,
+ .ioctl = rk3188_lcdc_ioctl,
+ .suspend = rk3188_lcdc_early_suspend,
+ .resume = rk3188_lcdc_early_resume,
+ .get_layer_state = rk3188_lcdc_get_layer_state,
+ .ovl_mgr = rk3188_lcdc_ovl_mgr,
+ .get_disp_info = rk3188_lcdc_get_disp_info,
+ .fps_mgr = rk3188_lcdc_fps_mgr,
+ .fb_get_layer = rk3188_fb_get_layer,
+ .fb_layer_remap = rk3188_fb_layer_remap,
+ .set_dsp_lut = rk3188_set_dsp_lut,
+};
+
+static irqreturn_t rk3188_lcdc_isr(int irq, void *dev_id)
+{
+ struct rk3188_lcdc_device *lcdc_dev =
+ (struct rk3188_lcdc_device *)dev_id;
+
+ lcdc_msk_reg(lcdc_dev, INT_STATUS, m_FS_INT_CLEAR, v_FS_INT_CLEAR(1));
+
+#if defined(WAIT_FOR_SYNC)
+ if(lcdc_dev->driver.num_buf < 3) //three buffer ,no need to wait for sync
+ {
+ spin_lock(&(lcdc_dev->driver.cpl_lock));
+ complete(&(lcdc_dev->driver.frame_done));
+ spin_unlock(&(lcdc_dev->driver.cpl_lock));
+ }
+#endif
+ return IRQ_HANDLED;
+}
+
+
+#if defined(CONFIG_PM)
+static int rk3188_lcdc_suspend(struct platform_device *pdev,
+ pm_message_t state)
+{
+ return 0;
+}
+
+static int rk3188_lcdc_resume(struct platform_device *pdev)
+{
+ return 0;
+}
+#else
+#define rk3188_lcdc_suspend NULL
+#define rk3188_lcdc_resume NULL
+#endif
+static int __devinit rk3188_lcdc_probe(struct platform_device *pdev)
+{
+ struct rk3188_lcdc_device *lcdc_dev = NULL;
+ struct device *dev = &pdev->dev;
+ rk_screen *screen;
+ struct rk29fb_info *screen_ctr_info;
+ struct resource *res = NULL;
+ struct resource *mem = NULL;
+ int ret = 0;
+
+ lcdc_dev = devm_kzalloc(dev,sizeof(struct rk3188_lcdc_device), GFP_KERNEL);
+ if(!lcdc_dev)
+ {
+ dev_err(&pdev->dev, ">>rk3188 lcdc device kmalloc fail!");
+ return -ENOMEM;
+ }
+ platform_set_drvdata(pdev, lcdc_dev);
+ lcdc_dev->id = pdev->id;
+ screen_ctr_info = (struct rk29fb_info * )pdev->dev.platform_data;
+ if(!screen_ctr_info)
+ {
+ dev_err(dev, "no platform data specified for screen control info!\n");
+ ret = -EINVAL;
+ goto err0;
+ }
+ screen = kzalloc(sizeof(rk_screen), GFP_KERNEL);
+ if(!screen)
+ {
+ dev_err(&pdev->dev, "rk screen kmalloc fail!");
+ ret = -ENOMEM;
+ goto err0;
+ }
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM,0);
+ if (res == NULL)
+ {
+ dev_err(&pdev->dev, "failed to get register resource for lcdc%d \n",lcdc_dev->id);
+ ret = -ENOENT;
+ goto err1;
+ }
+
+ lcdc_dev->reg_phy_base = res->start;
+ lcdc_dev->len = resource_size(res);
+ mem = request_mem_region(lcdc_dev->reg_phy_base,lcdc_dev->len, pdev->name);
+ if (!mem)
+ {
+ dev_err(&pdev->dev, "failed to request mem region for lcdc%d\n",lcdc_dev->id);
+ ret = -ENOENT;
+ goto err1;
+ }
+ lcdc_dev->regs = ioremap(lcdc_dev->reg_phy_base,lcdc_dev->len);
+ if (!lcdc_dev->regs)
+ {
+ dev_err(&pdev->dev, "cannot map register for lcdc%d\n",lcdc_dev->id);
+ ret = -ENXIO;
+ goto err2;
+ }
+
+ lcdc_dev->regsbak = kzalloc(lcdc_dev->len,GFP_KERNEL);
+ if(!lcdc_dev->regsbak)
+ {
+ dev_err(&pdev->dev, "failed to map memory for reg backup!\n");
+ ret = -ENOMEM;
+ goto err3;
+ }
+ lcdc_dev->dsp_lut_addr_base = (lcdc_dev->regs + DSP_LUT_ADDR);
+ printk("lcdc%d:reg_phy_base = 0x%08x,reg_vir_base:0x%p\n",pdev->id,lcdc_dev->reg_phy_base, lcdc_dev->regs);
+ lcdc_dev->driver.dev = dev;
+ lcdc_dev->driver.screen0 = screen;
+ lcdc_dev->driver.cur_screen = screen;
+ lcdc_dev->driver.screen_ctr_info = screen_ctr_info;
+
+ spin_lock_init(&lcdc_dev->reg_lock);
+
+ lcdc_dev->irq = platform_get_irq(pdev, 0);
+ if(lcdc_dev->irq < 0)
+ {
+ dev_err(&pdev->dev, "cannot find IRQ for lcdc%d\n",lcdc_dev->id);
+ goto err3;
+ }
+ ret = devm_request_irq(dev,lcdc_dev->irq, rk3188_lcdc_isr, IRQF_DISABLED,dev_name(dev),lcdc_dev);
+ if (ret)
+ {
+ dev_err(&pdev->dev, "cannot requeset irq %d - err %d\n", lcdc_dev->irq, ret);
+ ret = -EBUSY;
+ goto err3;
+ }
+ ret = rk_fb_register(&(lcdc_dev->driver),&lcdc_driver,lcdc_dev->id);
+ if(ret < 0)
+ {
+ dev_err(dev,"register fb for lcdc%d failed!\n",lcdc_dev->id);
+ goto err4;
+ }
+ printk("rk3188 lcdc%d probe ok!\n",lcdc_dev->id);
+
+ return 0;
+
+err4:
+ free_irq(lcdc_dev->irq,lcdc_dev);
+err3:
+ iounmap(lcdc_dev->regs);
+err2:
+ release_mem_region(lcdc_dev->reg_phy_base,lcdc_dev->len);
+err1:
+ kfree(screen);
+err0:
+ platform_set_drvdata(pdev, NULL);
+ kfree(lcdc_dev);
+
+ return ret;
+}
+
+static int __devexit rk3188_lcdc_remove(struct platform_device *pdev)
+{
+ return 0;
+}
+
+static void rk3188_lcdc_shutdown(struct platform_device *pdev)
+{
+
+}
+static struct platform_driver rk3188_lcdc_driver = {
+ .probe = rk3188_lcdc_probe,
+ .remove = __devexit_p(rk3188_lcdc_remove),
+ .driver = {
+ .name = "rk3188-lcdc",
+ .owner = THIS_MODULE,
+ },
+ .suspend = rk3188_lcdc_suspend,
+ .resume = rk3188_lcdc_resume,
+ .shutdown = rk3188_lcdc_shutdown,
+};
+static int __init rk3188_lcdc_module_init(void)
+{
+ return platform_driver_register(&rk3188_lcdc_driver);
+}
+
+static void __exit rk3188_lcdc_module_exit(void)
+{
+ platform_driver_unregister(&rk3188_lcdc_driver);
+}
+fs_initcall(rk3188_lcdc_module_init);
+module_exit(rk3188_lcdc_module_exit);
-#ifndef RK3188_LCDC_H_\r
-#define RK3188_LCDC_H_\r
-\r
-#include<linux/rk_fb.h>\r
-#include<linux/io.h>\r
-#include<linux/clk.h>\r
-\r
-\r
-/*******************register definition**********************/\r
-\r
-#define SYS_CTRL (0x00)\r
-#define m_WIN0_EN (1<<0)\r
-#define m_WIN1_EN (1<<1)\r
-#define m_HWC_EN (1<<2)\r
-#define m_WIN0_FORMAT (7<<3)\r
-#define m_WIN1_FORMAT (7<<6)\r
-#define m_HWC_COLOR_MODE (1<<9)\r
-#define m_HWC_SIZE (1<<10)\r
-#define m_WIN0_3D_EN (1<11)\r
-#define m_WIN0_3D_MODE (7<<12)\r
-#define m_WIN0_RB_SWAP (1<<15)\r
-#define m_WIN0_ALPHA_SWAP (1<<16)\r
-#define m_WIN0_Y8_SWAP (1<<17)\r
-#define m_WIN0_UV_SWAP (1<<18)\r
-#define m_WIN1_RB_SWAP (1<<19)\r
-#define m_WIN1_ALPHA_SWAP (1<<20)\r
-#define m_WIN1_BL_SWAP (1<<21)\r
-#define m_WIN0_OTSD_DISABLE (1<<22)\r
-#define m_WIN1_OTSD_DISABLE (1<<23)\r
-#define m_DMA_BURST_LENGTH (3<<24)\r
-#define m_HWC_LODAD_EN (1<<26)\r
-#define m_WIN1_LUT_EN (1<<27)\r
-#define m_DSP_LUT_EN (1<<28)\r
-#define m_DMA_STOP (1<<29)\r
-#define m_LCDC_STANDBY (1<<30)\r
-#define m_AUTO_GATING_EN (1<<31)\r
-#define v_WIN0_EN(x) (((x)&1)<<0)\r
-#define v_WIN1_EN(x) (((x)&1)<<1)\r
-#define v_HWC_EN(x) (((x)&1)<<2)\r
-#define v_WIN0_FORMAT(x) (((x)&7)<<3)\r
-#define v_WIN1_FORMAT(x) (((x)&7)<<6)\r
-#define v_HWC_COLOR_MODE(x) (((x)&1)<<9)\r
-#define v_HWC_SIZE(x) (((x)&1)<<10)\r
-#define v_WIN0_3D_EN(x) (((x)&1)<11)\r
-#define v_WIN0_3D_MODE(x) (((x)&7)<<12)\r
-#define v_WIN0_RB_SWAP(x) (((x)&1)<<15)\r
-#define v_WIN0_ALPHA_SWAP(x) (((x)&1)<<16)\r
-#define v_WIN0_Y8_SWAP(x) (((x)&1)<<17)\r
-#define v_WIN0_UV_SWAP(x) (((x)&1)<<18)\r
-#define v_WIN1_RB_SWAP(x) (((x)&1)<<19)\r
-#define v_WIN1_ALPHA_SWAP(x) (((x)&1)<<20)\r
-#define v_WIN1_BL_SWAP(x) (((x)&1)<<21)\r
-#define v_WIN0_OTSD_DISABLE(x) (((x)&1)<<22)\r
-#define v_WIN1_OTSD_DISABLE(x) (((x)&1)<<23)\r
-#define v_DMA_BURST_LENGTH(x) (((x)&3)<<24)\r
-#define v_HWC_LODAD_EN(x) (((x)&1)<<26)\r
-#define v_WIN1_LUT_EN(x) (((x)&1)<<27)\r
-#define v_DSP_LUT_EN(x) (((x)&1)<<28)\r
-#define v_DMA_STOP(x) (((x)&1)<<29)\r
-#define v_LCDC_STANDBY(x) (((x)&1)<<30)\r
-#define v_AUTO_GATING_EN(x) (((x)&1)<<31)\r
-\r
-\r
-#define DSP_CTRL0 (0x04)\r
-#define m_DSP_OUT_FORMAT (0x0f<<0)\r
-#define m_HSYNC_POL (1<<4)\r
-#define m_VSYNC_POL (1<<5)\r
-#define m_DEN_POL (1<<6)\r
-#define m_DCLK_POL (1<<7)\r
-#define m_WIN0_TOP (1<<8)\r
-#define m_DITHER_UP_EN (1<<9)\r
-#define m_DITHER_DOWN_MODE (1<<10)\r
-#define m_DITHER_DOWN_EN (1<<11)\r
-#define m_INTERLACE_DSP_EN (1<<12)\r
-#define m_INTERLACE_POL (1<<13)\r
-#define m_WIN0_INTERLACE_EN (1<<14)\r
-#define m_WIN1_INTERLACE_EN (1<<15)\r
-#define m_WIN0_YRGB_DEFLICK_EN (1<<16)\r
-#define m_WIN0_CBR_DEFLICK_EN (1<<17)\r
-#define m_WIN0_ALPHA_MODE (1<<18)\r
-#define m_WIN1_ALPHA_MODE (1<<19)\r
-#define m_WIN0_CSC_MODE (3<<20)\r
-#define m_WIN1_CSC_MODE (1<<22)\r
-#define m_WIN0_YUV_CLIP (1<<23)\r
-#define m_DSP_CCIR656_AVG (1<<24)\r
-#define m_DCLK_OUTPUT_MODE (1<<25)\r
-#define m_DCLK_PHASE_LOCK (1<<26)\r
-#define m_DITHER_DOWN_SEL (3<<27)\r
-#define m_ALPHA_MODE_SEL0 (1<<29)\r
-#define m_ALPHA_MODE_SEL1 (1<<30)\r
-#define m_DIFF_DCLK_EN (1<<31)\r
-#define v_DSP_OUT_FORMAT(x) (((x)&0x0f)<<0)\r
-#define v_HSYNC_POL(x) (((x)&1)<<4)\r
-#define v_VSYNC_POL(x) (((x)&1)<<5)\r
-#define v_DEN_POL(x) (((x)&1)<<6)\r
-#define v_DCLK_POL(x) (((x)&1)<<7)\r
-#define v_WIN0_TOP(x) (((x)&1)<<8)\r
-#define v_DITHER_UP_EN(x) (((x)&1)<<9)\r
-#define v_DITHER_DOWN_MODE(x) (((x)&1)<<10)\r
-#define v_DITHER_DOWN_EN(x) (((x)&1)<<11)\r
-#define v_INTERLACE_DSP_EN(x) (((x)&1)<<12)\r
-#define v_INTERLACE_POL(x) (((x)&1)<<13)\r
-#define v_WIN0_INTERLACE_EN(x) (((x)&1)<<14)\r
-#define v_WIN1_INTERLACE_EN(x) (((x)&1)<<15)\r
-#define v_WIN0_YRGB_DEFLICK_EN(x) (((x)&1)<<16)\r
-#define v_WIN0_CBR_DEFLICK_EN(x) (((x)&1)<<17)\r
-#define v_WIN0_ALPHA_MODE(x) (((x)&1)<<18)\r
-#define v_WIN1_ALPHA_MODE(x) (((x)&1)<<19)\r
-#define v_WIN0_CSC_MODE(x) (((x)&3)<<20)\r
-#define v_WIN1_CSC_MODE(x) (((x)&1)<<22)\r
-#define v_WIN0_YUV_CLIP(x) (((x)&1)<<23)\r
-#define v_DSP_CCIR656_AVG(x) (((x)&1)<<24)\r
-#define v_DCLK_OUTPUT_MODE(x) (((x)&1)<<25)\r
-#define v_DCLK_PHASE_LOCK(x) (((x)&1)<<26)\r
-#define v_DITHER_DOWN_SEL(x) (((x)&1)<<27)\r
-#define v_ALPHA_MODE_SEL0(x) (((x)&1)<<29)\r
-#define v_ALPHA_MODE_SEL1(x) (((x)&1)<<30)\r
-#define v_DIFF_DCLK_EN(x) (((x)&1)<<31)\r
-\r
-\r
-#define DSP_CTRL1 (0x08)\r
-#define m_BG_COLOR (0xffffff<<0)\r
-#define m_BG_B (0xff<<0)\r
-#define m_BG_G (0xff<<8)\r
-#define m_BG_R (0xff<<16)\r
-#define m_BLANK_EN (1<<24)\r
-#define m_BLACK_EN (1<<25)\r
-#define m_DSP_BG_SWAP (1<<26)\r
-#define m_DSP_RB_SWAP (1<<27)\r
-#define m_DSP_RG_SWAP (1<<28)\r
-#define m_DSP_DELTA_SWAP (1<<29)\r
-#define m_DSP_DUMMY_SWAP (1<<30)\r
-#define m_DSP_OUT_ZERO (1<<31)\r
-#define v_BG_COLOR(x) (((x)&0xffffff)<<0)\r
-#define v_BG_B(x) (((x)&0xff)<<0)\r
-#define v_BG_G(x) (((x)&0xff)<<8)\r
-#define v_BG_R(x) (((x)&0xff)<<16)\r
-#define v_BLANK_EN(x) (((x)&1)<<24)\r
-#define v_BLACK_EN(x) (((x)&1)<<25)\r
-#define v_DSP_BG_SWAP(x) (((x)&1)<<26)\r
-#define v_DSP_RB_SWAP(x) (((x)&1)<<27)\r
-#define v_DSP_RG_SWAP(x) (((x)&1)<<28)\r
-#define v_DSP_DELTA_SWAP(x) (((x)&1)<<29)\r
-#define v_DSP_DUMMY_SWAP(x) (((x)&1)<<30)\r
-#define v_DSP_OUT_ZERO(x) (((x)&1)<<31)\r
-\r
-\r
-#define MCU_CTRL (0x0c)\r
-#define m_MCU_PIX_TOTAL (0x3f<<0)\r
-#define m_MCU_CS_ST (0x0f<<6)\r
-#define m_MCU_CS_END (0x3f<<10)\r
-#define m_MCU_RW_ST (0x0f<<16)\r
-#define m_MCU_RW_END (0x3f<<20)\r
-#define m_MCU_CLK_SEL (1<<26)\r
-#define m_MCU_HOLD_MODE (1<<27)\r
-#define m_MCU_FS_HOLD_STA (1<<28)\r
-#define m_MCU_RS_SELECT (1<<29)\r
-#define m_MCU_BYPASS (1<<30)\r
-#define m_MCU_TYPE (1<<31)\r
-\r
-#define v_MCU_PIX_TOTAL(x) (((x)&0x3f)<<0)\r
-#define v_MCU_CS_ST(x) (((x)&0x0f)<<6)\r
-#define v_MCU_CS_END(x) (((x)&0x3f)<<10)\r
-#define v_MCU_RW_ST(x) (((x)&0x0f)<<16)\r
-#define v_MCU_RW_END(x) (((x)&0x3f)<<20)\r
-#define v_MCU_CLK_SEL(x) (((x)&1)<<26)\r
-#define v_MCU_HOLD_MODE(x) (((x)&1)<<27)\r
-#define v_MCU_FS_HOLD_STA(x) (((x)&1)<<28)\r
-#define v_MCU_RS_SELECT(x) (((x)&1)<<29)\r
-#define v_MCU_BYPASS(x) (((x)&1)<<30)\r
-#define v_MCU_TYPE(x) (((x)&1)<<31)\r
-\r
-#define INT_STATUS (0x10)\r
-#define m_HS_INT_STA (1<<0) //status\r
-#define m_FS_INT_STA (1<<1)\r
-#define m_LF_INT_STA (1<<2)\r
-#define m_BUS_ERR_INT_STA (1<<3)\r
-#define m_HS_INT_EN (1<<4) //enable\r
-#define m_FS_INT_EN (1<<5)\r
-#define m_LF_INT_EN (1<<6)\r
-#define m_BUS_ERR_INT_EN (1<<7)\r
-#define m_HS_INT_CLEAR (1<<8) //auto clear\r
-#define m_FS_INT_CLEAR (1<<9)\r
-#define m_LF_INT_CLEAR (1<<10)\r
-#define m_BUS_ERR_INT_CLEAR (1<<11)\r
-#define m_LINE_FLAG_NUM (0xfff<<12)\r
-#define v_HS_INT_EN(x) (((x)&1)<<4)\r
-#define v_FS_INT_EN(x) (((x)&1)<<5)\r
-#define v_LF_INT_EN(x) (((x)&1)<<6)\r
-#define v_BUS_ERR_INT_EN(x) (((x)&1)<<7)\r
-#define v_HS_INT_CLEAR(x) (((x)&1)<<8)\r
-#define v_FS_INT_CLEAR(x) (((x)&1)<<9)\r
-#define v_LF_INT_CLEAR(x) (((x)&1)<<10)\r
-#define v_BUS_ERR_INT_CLEAR(x) (((x)&1)<<11)\r
-#define v_LINE_FLAG_NUM(x) (((x)&0xfff)<<12)\r
-\r
-\r
-#define ALPHA_CTRL (0x14)\r
-#define m_WIN0_ALPHA_EN (1<<0)\r
-#define m_WIN1_ALPAH_EN (1<<1)\r
-#define m_HWC_ALPAH_EN (1<<2)\r
-#define m_WIN0_ALPHA_VAL (0xff<<4)\r
-#define m_WIN1_ALPHA_VAL (0xff<<12)\r
-#define m_HWC_ALPAH_VAL (0x0f<<20)\r
-#define v_WIN0_ALPHA_EN(x) (((x)&1)<<0)\r
-#define v_WIN1_ALPAH_EN(x) (((x)&1)<<1)\r
-#define v_HWC_ALPAH_EN(x) (((x)&1)<<2)\r
-#define v_WIN0_ALPHA_VAL(x) (((x)&0xff)<<4)\r
-#define v_WIN1_ALPHA_VAL(x) (((x)&0xff)<<12)\r
-#define v_HWC_ALPAH_VAL(x) (((x)&0x0f)<<20)\r
-\r
-#define WIN0_COLOR_KEY (0x18)\r
-#define m_COLOR_KEY_VAL (0xffffff<<0)\r
-#define m_COLOR_KEY_EN (1<<24)\r
-#define v_COLOR_KEY_VAL(x) (((x)&0xffffff)<<0)\r
-#define v_COLOR_KEY_EN(x) (((x)&1)<<24)\r
-\r
-#define WIN1_COLOR_KEY (0x1C)\r
-\r
-\r
-#define WIN0_YRGB_MST0 (0x20)\r
-#define WIN0_CBR_MST0 (0x24)\r
-#define WIN0_YRGB_MST1 (0x28)\r
-#define WIN0_CBR_MST1 (0x2C)\r
-#define WIN_VIR (0x30)\r
-#define m_WIN0_VIR (0x1fff << 0)\r
-#define m_WIN1_VIR (0x1fff << 16)\r
-#define v_ARGB888_VIRWIDTH(x) (((x)&0x1fff)<<0)\r
-#define v_RGB888_VIRWIDTH(x) (((((x*3)>>2)+((x)%3))&0x1fff)<<0)\r
-#define v_RGB565_VIRWIDTH(x) ((DIV_ROUND_UP(x,2)&0x1fff)<<0)\r
-#define v_YUV_VIRWIDTH(x) ((DIV_ROUND_UP(x,4)&0x1fff)<<0)\r
-#define v_WIN1_ARGB888_VIRWIDTH(x) (((x)&0x1fff)<<0)\r
-#define v_WIN1_RGB888_VIRWIDTH(x) (((((x*3)>>2)+((x)%3))&0x1fff)<<0)\r
-#define v_WIN1_RGB565_VIRWIDTH(x) ((DIV_ROUND_UP(x,2)&0x1fff)<<0)\r
-\r
-\r
-\r
-#define WIN0_ACT_INFO (0x34)\r
-#define m_ACT_WIDTH (0x1fff<<0)\r
-#define m_ACT_HEIGHT (0x1fff<<16)\r
-#define v_ACT_WIDTH(x) (((x)&0x1fff)<<0)\r
-#define v_ACT_HEIGHT(x) (((x)&0x1fff)<<16)\r
-\r
-#define WIN0_DSP_INFO (0x38)\r
-#define v_DSP_WIDTH(x) (((x-1)&0x7ff)<<0)\r
-#define v_DSP_HEIGHT(x) (((x-1)&0x7ff)<<16)\r
-\r
-#define WIN0_DSP_ST (0x3C)\r
-#define v_DSP_STX(x) (((x)&0xfff)<<0)\r
-#define v_DSP_STY(x) (((x)&0xfff)<<16)\r
-\r
-#define WIN0_SCL_FACTOR_YRGB (0x40)\r
-#define v_X_SCL_FACTOR(x) (((x)&0xffff)<<0)\r
-#define v_Y_SCL_FACTOR(x) (((x)&0xffff)<<16)\r
-\r
-#define WIN0_SCL_FACTOR_CBR (0x44)\r
-#define WIN0_SCL_OFFSET (0x48)\r
-#define WIN1_MST (0x4C)\r
-#define WIN1_DSP_INFO (0x50)\r
-#define WIN1_DSP_ST (0x54)\r
-#define HWC_MST (0x58)\r
-#define HWC_DSP_ST (0x5C)\r
-#define HWC_COLOR_LUT0 (0x60)\r
-#define HWC_COLOR_LUT1 (0x64)\r
-#define HWC_COLOR_LUT2 (0x68)\r
-#define DSP_HTOTAL_HS_END (0x6C)\r
-#define v_HSYNC(x) (((x)&0xfff)<<0) //hsync pulse width\r
-#define v_HORPRD(x) (((x)&0xfff)<<16) //horizontal period\r
-\r
-#define DSP_HACT_ST_END (0x70)\r
-#define v_HAEP(x) (((x)&0xfff)<<0) //horizontal active end point\r
-#define v_HASP(x) (((x)&0xfff)<<16) //horizontal active start point\r
-\r
-#define DSP_VTOTAL_VS_END (0x74)\r
-#define v_VSYNC(x) (((x)&0xfff)<<0)\r
-#define v_VERPRD(x) (((x)&0xfff)<<16)\r
-#define DSP_VACT_ST_END (0x78)\r
-#define v_VAEP(x) (((x)&0xfff)<<0)\r
-#define v_VASP(x) (((x)&0xfff)<<16)\r
-\r
-#define DSP_VS_ST_END_F1 (0x7C)\r
-#define DSP_VACT_ST_END_F1 (0x80)\r
-#define REG_CFG_DONE (0x90)\r
-#define MCU_BYPASS_WPORT (0x100)\r
-#define MCU_BYPASS_RPORT (0x200)\r
-#define WIN1_LUT_ADDR (0x400)\r
-#define DSP_LUT_ADDR (0x800)\r
-\r
-\r
-#define CalScale(x, y) ((((u32)x)*0x1000)/y)\r
-\r
-struct rk3188_lcdc_device{\r
- int id;\r
- struct rk_lcdc_device_driver driver;\r
- rk_screen *screen;\r
-\r
- void __iomem *regs;\r
- void *regsbak; //back up reg\r
- u32 reg_phy_base; // physical basic address of lcdc register\r
- u32 len; // physical map length of lcdc register\r
- spinlock_t reg_lock; //one time only one process allowed to config the register\r
- \r
- int __iomem *dsp_lut_addr_base;\r
- \r
- \r
- bool clk_on; //if aclk or hclk is closed ,acess to register is not allowed\r
- u8 atv_layer_cnt; //active layer counter,when atv_layer_cnt = 0,disable lcdc\r
-\r
- unsigned int irq;\r
-\r
- struct clk *pd; //lcdc power domain\r
- struct clk *hclk; //lcdc AHP clk\r
- struct clk *dclk; //lcdc dclk\r
- struct clk *aclk; //lcdc share memory frequency\r
- u32 pixclock; \r
-};\r
-\r
-\r
-\r
-static inline void lcdc_writel(struct rk3188_lcdc_device *lcdc_dev,u32 offset,u32 v)\r
-{\r
- u32 *_pv = (u32*)lcdc_dev->regsbak; \r
- _pv += (offset >> 2); \r
- *_pv = v;\r
- writel_relaxed(v,lcdc_dev->regs+offset); \r
-}\r
-\r
-static inline u32 lcdc_readl(struct rk3188_lcdc_device *lcdc_dev,u32 offset)\r
-{\r
- return readl_relaxed(lcdc_dev->regs+offset);\r
-}\r
-\r
-static inline u32 lcdc_read_bit(struct rk3188_lcdc_device *lcdc_dev,u32 offset,u32 msk) \r
-{\r
- u32 _v = readl_relaxed(lcdc_dev->regs+offset); \r
- _v &= msk;\r
- return (_v >> msk); \r
-}\r
-\r
-static inline void lcdc_set_bit(struct rk3188_lcdc_device *lcdc_dev,u32 offset,u32 msk) \r
-{\r
- u32* _pv = (u32*)lcdc_dev->regsbak; \r
- _pv += (offset >> 2); \r
- (*_pv) |= msk; \r
- writel_relaxed(*_pv,lcdc_dev->regs + offset); \r
-} \r
-\r
-static inline void lcdc_clr_bit(struct rk3188_lcdc_device *lcdc_dev,u32 offset,u32 msk)\r
-{\r
- u32* _pv = (u32*)lcdc_dev->regsbak; \r
- _pv += (offset >> 2); \r
- (*_pv) &= (~msk); \r
- writel_relaxed(*_pv,lcdc_dev->regs + offset); \r
-} \r
-\r
-static inline void lcdc_msk_reg(struct rk3188_lcdc_device *lcdc_dev,u32 offset,u32 msk,u32 v)\r
-{\r
- u32 *_pv = (u32*)lcdc_dev->regsbak; \r
- _pv += (offset >> 2); \r
- (*_pv) &= (~msk); \r
- (*_pv) |= v; \r
- writel_relaxed(*_pv,lcdc_dev->regs+offset); \r
-}\r
-\r
-static inline void lcdc_cfg_done(struct rk3188_lcdc_device *lcdc_dev) \r
-{\r
- writel_relaxed(0x01,lcdc_dev->regs+REG_CFG_DONE); \r
- dsb(); \r
-} \r
-\r
-#endif\r
+#ifndef RK3188_LCDC_H_
+#define RK3188_LCDC_H_
+
+#include<linux/rk_fb.h>
+#include<linux/io.h>
+#include<linux/clk.h>
+
+
+/*******************register definition**********************/
+
+#define SYS_CTRL (0x00)
+#define m_WIN0_EN (1<<0)
+#define m_WIN1_EN (1<<1)
+#define m_HWC_EN (1<<2)
+#define m_WIN0_FORMAT (7<<3)
+#define m_WIN1_FORMAT (7<<6)
+#define m_HWC_COLOR_MODE (1<<9)
+#define m_HWC_SIZE (1<<10)
+#define m_WIN0_3D_EN (1<11)
+#define m_WIN0_3D_MODE (7<<12)
+#define m_WIN0_RB_SWAP (1<<15)
+#define m_WIN0_ALPHA_SWAP (1<<16)
+#define m_WIN0_Y8_SWAP (1<<17)
+#define m_WIN0_UV_SWAP (1<<18)
+#define m_WIN1_RB_SWAP (1<<19)
+#define m_WIN1_ALPHA_SWAP (1<<20)
+#define m_WIN1_BL_SWAP (1<<21)
+#define m_WIN0_OTSD_DISABLE (1<<22)
+#define m_WIN1_OTSD_DISABLE (1<<23)
+#define m_DMA_BURST_LENGTH (3<<24)
+#define m_HWC_LODAD_EN (1<<26)
+#define m_WIN1_LUT_EN (1<<27)
+#define m_DSP_LUT_EN (1<<28)
+#define m_DMA_STOP (1<<29)
+#define m_LCDC_STANDBY (1<<30)
+#define m_AUTO_GATING_EN (1<<31)
+#define v_WIN0_EN(x) (((x)&1)<<0)
+#define v_WIN1_EN(x) (((x)&1)<<1)
+#define v_HWC_EN(x) (((x)&1)<<2)
+#define v_WIN0_FORMAT(x) (((x)&7)<<3)
+#define v_WIN1_FORMAT(x) (((x)&7)<<6)
+#define v_HWC_COLOR_MODE(x) (((x)&1)<<9)
+#define v_HWC_SIZE(x) (((x)&1)<<10)
+#define v_WIN0_3D_EN(x) (((x)&1)<11)
+#define v_WIN0_3D_MODE(x) (((x)&7)<<12)
+#define v_WIN0_RB_SWAP(x) (((x)&1)<<15)
+#define v_WIN0_ALPHA_SWAP(x) (((x)&1)<<16)
+#define v_WIN0_Y8_SWAP(x) (((x)&1)<<17)
+#define v_WIN0_UV_SWAP(x) (((x)&1)<<18)
+#define v_WIN1_RB_SWAP(x) (((x)&1)<<19)
+#define v_WIN1_ALPHA_SWAP(x) (((x)&1)<<20)
+#define v_WIN1_BL_SWAP(x) (((x)&1)<<21)
+#define v_WIN0_OTSD_DISABLE(x) (((x)&1)<<22)
+#define v_WIN1_OTSD_DISABLE(x) (((x)&1)<<23)
+#define v_DMA_BURST_LENGTH(x) (((x)&3)<<24)
+#define v_HWC_LODAD_EN(x) (((x)&1)<<26)
+#define v_WIN1_LUT_EN(x) (((x)&1)<<27)
+#define v_DSP_LUT_EN(x) (((x)&1)<<28)
+#define v_DMA_STOP(x) (((x)&1)<<29)
+#define v_LCDC_STANDBY(x) (((x)&1)<<30)
+#define v_AUTO_GATING_EN(x) (((x)&1)<<31)
+
+
+#define DSP_CTRL0 (0x04)
+#define m_DSP_OUT_FORMAT (0x0f<<0)
+#define m_HSYNC_POL (1<<4)
+#define m_VSYNC_POL (1<<5)
+#define m_DEN_POL (1<<6)
+#define m_DCLK_POL (1<<7)
+#define m_WIN0_TOP (1<<8)
+#define m_DITHER_UP_EN (1<<9)
+#define m_DITHER_DOWN_MODE (1<<10)
+#define m_DITHER_DOWN_EN (1<<11)
+#define m_INTERLACE_DSP_EN (1<<12)
+#define m_INTERLACE_POL (1<<13)
+#define m_WIN0_INTERLACE_EN (1<<14)
+#define m_WIN1_INTERLACE_EN (1<<15)
+#define m_WIN0_YRGB_DEFLICK_EN (1<<16)
+#define m_WIN0_CBR_DEFLICK_EN (1<<17)
+#define m_WIN0_ALPHA_MODE (1<<18)
+#define m_WIN1_ALPHA_MODE (1<<19)
+#define m_WIN0_CSC_MODE (3<<20)
+#define m_WIN1_CSC_MODE (1<<22)
+#define m_WIN0_YUV_CLIP (1<<23)
+#define m_DSP_CCIR656_AVG (1<<24)
+#define m_DCLK_OUTPUT_MODE (1<<25)
+#define m_DCLK_PHASE_LOCK (1<<26)
+#define m_DITHER_DOWN_SEL (3<<27)
+#define m_ALPHA_MODE_SEL0 (1<<29)
+#define m_ALPHA_MODE_SEL1 (1<<30)
+#define m_DIFF_DCLK_EN (1<<31)
+#define v_DSP_OUT_FORMAT(x) (((x)&0x0f)<<0)
+#define v_HSYNC_POL(x) (((x)&1)<<4)
+#define v_VSYNC_POL(x) (((x)&1)<<5)
+#define v_DEN_POL(x) (((x)&1)<<6)
+#define v_DCLK_POL(x) (((x)&1)<<7)
+#define v_WIN0_TOP(x) (((x)&1)<<8)
+#define v_DITHER_UP_EN(x) (((x)&1)<<9)
+#define v_DITHER_DOWN_MODE(x) (((x)&1)<<10)
+#define v_DITHER_DOWN_EN(x) (((x)&1)<<11)
+#define v_INTERLACE_DSP_EN(x) (((x)&1)<<12)
+#define v_INTERLACE_POL(x) (((x)&1)<<13)
+#define v_WIN0_INTERLACE_EN(x) (((x)&1)<<14)
+#define v_WIN1_INTERLACE_EN(x) (((x)&1)<<15)
+#define v_WIN0_YRGB_DEFLICK_EN(x) (((x)&1)<<16)
+#define v_WIN0_CBR_DEFLICK_EN(x) (((x)&1)<<17)
+#define v_WIN0_ALPHA_MODE(x) (((x)&1)<<18)
+#define v_WIN1_ALPHA_MODE(x) (((x)&1)<<19)
+#define v_WIN0_CSC_MODE(x) (((x)&3)<<20)
+#define v_WIN1_CSC_MODE(x) (((x)&1)<<22)
+#define v_WIN0_YUV_CLIP(x) (((x)&1)<<23)
+#define v_DSP_CCIR656_AVG(x) (((x)&1)<<24)
+#define v_DCLK_OUTPUT_MODE(x) (((x)&1)<<25)
+#define v_DCLK_PHASE_LOCK(x) (((x)&1)<<26)
+#define v_DITHER_DOWN_SEL(x) (((x)&1)<<27)
+#define v_ALPHA_MODE_SEL0(x) (((x)&1)<<29)
+#define v_ALPHA_MODE_SEL1(x) (((x)&1)<<30)
+#define v_DIFF_DCLK_EN(x) (((x)&1)<<31)
+
+
+#define DSP_CTRL1 (0x08)
+#define m_BG_COLOR (0xffffff<<0)
+#define m_BG_B (0xff<<0)
+#define m_BG_G (0xff<<8)
+#define m_BG_R (0xff<<16)
+#define m_BLANK_EN (1<<24)
+#define m_BLACK_EN (1<<25)
+#define m_DSP_BG_SWAP (1<<26)
+#define m_DSP_RB_SWAP (1<<27)
+#define m_DSP_RG_SWAP (1<<28)
+#define m_DSP_DELTA_SWAP (1<<29)
+#define m_DSP_DUMMY_SWAP (1<<30)
+#define m_DSP_OUT_ZERO (1<<31)
+#define v_BG_COLOR(x) (((x)&0xffffff)<<0)
+#define v_BG_B(x) (((x)&0xff)<<0)
+#define v_BG_G(x) (((x)&0xff)<<8)
+#define v_BG_R(x) (((x)&0xff)<<16)
+#define v_BLANK_EN(x) (((x)&1)<<24)
+#define v_BLACK_EN(x) (((x)&1)<<25)
+#define v_DSP_BG_SWAP(x) (((x)&1)<<26)
+#define v_DSP_RB_SWAP(x) (((x)&1)<<27)
+#define v_DSP_RG_SWAP(x) (((x)&1)<<28)
+#define v_DSP_DELTA_SWAP(x) (((x)&1)<<29)
+#define v_DSP_DUMMY_SWAP(x) (((x)&1)<<30)
+#define v_DSP_OUT_ZERO(x) (((x)&1)<<31)
+
+
+#define MCU_CTRL (0x0c)
+#define m_MCU_PIX_TOTAL (0x3f<<0)
+#define m_MCU_CS_ST (0x0f<<6)
+#define m_MCU_CS_END (0x3f<<10)
+#define m_MCU_RW_ST (0x0f<<16)
+#define m_MCU_RW_END (0x3f<<20)
+#define m_MCU_CLK_SEL (1<<26)
+#define m_MCU_HOLD_MODE (1<<27)
+#define m_MCU_FS_HOLD_STA (1<<28)
+#define m_MCU_RS_SELECT (1<<29)
+#define m_MCU_BYPASS (1<<30)
+#define m_MCU_TYPE (1<<31)
+
+#define v_MCU_PIX_TOTAL(x) (((x)&0x3f)<<0)
+#define v_MCU_CS_ST(x) (((x)&0x0f)<<6)
+#define v_MCU_CS_END(x) (((x)&0x3f)<<10)
+#define v_MCU_RW_ST(x) (((x)&0x0f)<<16)
+#define v_MCU_RW_END(x) (((x)&0x3f)<<20)
+#define v_MCU_CLK_SEL(x) (((x)&1)<<26)
+#define v_MCU_HOLD_MODE(x) (((x)&1)<<27)
+#define v_MCU_FS_HOLD_STA(x) (((x)&1)<<28)
+#define v_MCU_RS_SELECT(x) (((x)&1)<<29)
+#define v_MCU_BYPASS(x) (((x)&1)<<30)
+#define v_MCU_TYPE(x) (((x)&1)<<31)
+
+#define INT_STATUS (0x10)
+#define m_HS_INT_STA (1<<0) //status
+#define m_FS_INT_STA (1<<1)
+#define m_LF_INT_STA (1<<2)
+#define m_BUS_ERR_INT_STA (1<<3)
+#define m_HS_INT_EN (1<<4) //enable
+#define m_FS_INT_EN (1<<5)
+#define m_LF_INT_EN (1<<6)
+#define m_BUS_ERR_INT_EN (1<<7)
+#define m_HS_INT_CLEAR (1<<8) //auto clear
+#define m_FS_INT_CLEAR (1<<9)
+#define m_LF_INT_CLEAR (1<<10)
+#define m_BUS_ERR_INT_CLEAR (1<<11)
+#define m_LINE_FLAG_NUM (0xfff<<12)
+#define v_HS_INT_EN(x) (((x)&1)<<4)
+#define v_FS_INT_EN(x) (((x)&1)<<5)
+#define v_LF_INT_EN(x) (((x)&1)<<6)
+#define v_BUS_ERR_INT_EN(x) (((x)&1)<<7)
+#define v_HS_INT_CLEAR(x) (((x)&1)<<8)
+#define v_FS_INT_CLEAR(x) (((x)&1)<<9)
+#define v_LF_INT_CLEAR(x) (((x)&1)<<10)
+#define v_BUS_ERR_INT_CLEAR(x) (((x)&1)<<11)
+#define v_LINE_FLAG_NUM(x) (((x)&0xfff)<<12)
+
+
+#define ALPHA_CTRL (0x14)
+#define m_WIN0_ALPHA_EN (1<<0)
+#define m_WIN1_ALPAH_EN (1<<1)
+#define m_HWC_ALPAH_EN (1<<2)
+#define m_WIN0_ALPHA_VAL (0xff<<4)
+#define m_WIN1_ALPHA_VAL (0xff<<12)
+#define m_HWC_ALPAH_VAL (0x0f<<20)
+#define v_WIN0_ALPHA_EN(x) (((x)&1)<<0)
+#define v_WIN1_ALPAH_EN(x) (((x)&1)<<1)
+#define v_HWC_ALPAH_EN(x) (((x)&1)<<2)
+#define v_WIN0_ALPHA_VAL(x) (((x)&0xff)<<4)
+#define v_WIN1_ALPHA_VAL(x) (((x)&0xff)<<12)
+#define v_HWC_ALPAH_VAL(x) (((x)&0x0f)<<20)
+
+#define WIN0_COLOR_KEY (0x18)
+#define m_COLOR_KEY_VAL (0xffffff<<0)
+#define m_COLOR_KEY_EN (1<<24)
+#define v_COLOR_KEY_VAL(x) (((x)&0xffffff)<<0)
+#define v_COLOR_KEY_EN(x) (((x)&1)<<24)
+
+#define WIN1_COLOR_KEY (0x1C)
+
+
+#define WIN0_YRGB_MST0 (0x20)
+#define WIN0_CBR_MST0 (0x24)
+#define WIN0_YRGB_MST1 (0x28)
+#define WIN0_CBR_MST1 (0x2C)
+#define WIN_VIR (0x30)
+#define m_WIN0_VIR (0x1fff << 0)
+#define m_WIN1_VIR (0x1fff << 16)
+#define v_ARGB888_VIRWIDTH(x) (((x)&0x1fff)<<0)
+#define v_RGB888_VIRWIDTH(x) (((((x*3)>>2)+((x)%3))&0x1fff)<<0)
+#define v_RGB565_VIRWIDTH(x) ((DIV_ROUND_UP(x,2)&0x1fff)<<0)
+#define v_YUV_VIRWIDTH(x) ((DIV_ROUND_UP(x,4)&0x1fff)<<0)
+#define v_WIN1_ARGB888_VIRWIDTH(x) (((x)&0x1fff)<<0)
+#define v_WIN1_RGB888_VIRWIDTH(x) (((((x*3)>>2)+((x)%3))&0x1fff)<<0)
+#define v_WIN1_RGB565_VIRWIDTH(x) ((DIV_ROUND_UP(x,2)&0x1fff)<<0)
+
+
+
+#define WIN0_ACT_INFO (0x34)
+#define m_ACT_WIDTH (0x1fff<<0)
+#define m_ACT_HEIGHT (0x1fff<<16)
+#define v_ACT_WIDTH(x) (((x)&0x1fff)<<0)
+#define v_ACT_HEIGHT(x) (((x)&0x1fff)<<16)
+
+#define WIN0_DSP_INFO (0x38)
+#define v_DSP_WIDTH(x) (((x-1)&0x7ff)<<0)
+#define v_DSP_HEIGHT(x) (((x-1)&0x7ff)<<16)
+
+#define WIN0_DSP_ST (0x3C)
+#define v_DSP_STX(x) (((x)&0xfff)<<0)
+#define v_DSP_STY(x) (((x)&0xfff)<<16)
+
+#define WIN0_SCL_FACTOR_YRGB (0x40)
+#define v_X_SCL_FACTOR(x) (((x)&0xffff)<<0)
+#define v_Y_SCL_FACTOR(x) (((x)&0xffff)<<16)
+
+#define WIN0_SCL_FACTOR_CBR (0x44)
+#define WIN0_SCL_OFFSET (0x48)
+#define WIN1_MST (0x4C)
+#define WIN1_DSP_INFO (0x50)
+#define WIN1_DSP_ST (0x54)
+#define HWC_MST (0x58)
+#define HWC_DSP_ST (0x5C)
+#define HWC_COLOR_LUT0 (0x60)
+#define HWC_COLOR_LUT1 (0x64)
+#define HWC_COLOR_LUT2 (0x68)
+#define DSP_HTOTAL_HS_END (0x6C)
+#define v_HSYNC(x) (((x)&0xfff)<<0) //hsync pulse width
+#define v_HORPRD(x) (((x)&0xfff)<<16) //horizontal period
+
+#define DSP_HACT_ST_END (0x70)
+#define v_HAEP(x) (((x)&0xfff)<<0) //horizontal active end point
+#define v_HASP(x) (((x)&0xfff)<<16) //horizontal active start point
+
+#define DSP_VTOTAL_VS_END (0x74)
+#define v_VSYNC(x) (((x)&0xfff)<<0)
+#define v_VERPRD(x) (((x)&0xfff)<<16)
+#define DSP_VACT_ST_END (0x78)
+#define v_VAEP(x) (((x)&0xfff)<<0)
+#define v_VASP(x) (((x)&0xfff)<<16)
+
+#define DSP_VS_ST_END_F1 (0x7C)
+#define DSP_VACT_ST_END_F1 (0x80)
+#define REG_CFG_DONE (0x90)
+#define MCU_BYPASS_WPORT (0x100)
+#define MCU_BYPASS_RPORT (0x200)
+#define WIN1_LUT_ADDR (0x400)
+#define DSP_LUT_ADDR (0x800)
+
+
+#define CalScale(x, y) ((((u32)x)*0x1000)/y)
+
+struct rk3188_lcdc_device{
+ int id;
+ struct rk_lcdc_device_driver driver;
+ rk_screen *screen;
+
+ void __iomem *regs;
+ void *regsbak; //back up reg
+ u32 reg_phy_base; // physical basic address of lcdc register
+ u32 len; // physical map length of lcdc register
+ spinlock_t reg_lock; //one time only one process allowed to config the register
+
+ int __iomem *dsp_lut_addr_base;
+
+
+ bool clk_on; //if aclk or hclk is closed ,acess to register is not allowed
+ u8 atv_layer_cnt; //active layer counter,when atv_layer_cnt = 0,disable lcdc
+
+ unsigned int irq;
+
+ struct clk *pd; //lcdc power domain
+ struct clk *hclk; //lcdc AHP clk
+ struct clk *dclk; //lcdc dclk
+ struct clk *aclk; //lcdc share memory frequency
+ u32 pixclock;
+};
+
+
+
+static inline void lcdc_writel(struct rk3188_lcdc_device *lcdc_dev,u32 offset,u32 v)
+{
+ u32 *_pv = (u32*)lcdc_dev->regsbak;
+ _pv += (offset >> 2);
+ *_pv = v;
+ writel_relaxed(v,lcdc_dev->regs+offset);
+}
+
+static inline u32 lcdc_readl(struct rk3188_lcdc_device *lcdc_dev,u32 offset)
+{
+ return readl_relaxed(lcdc_dev->regs+offset);
+}
+
+static inline u32 lcdc_read_bit(struct rk3188_lcdc_device *lcdc_dev,u32 offset,u32 msk)
+{
+ u32 _v = readl_relaxed(lcdc_dev->regs+offset);
+ _v &= msk;
+ return (_v >> msk);
+}
+
+static inline void lcdc_set_bit(struct rk3188_lcdc_device *lcdc_dev,u32 offset,u32 msk)
+{
+ u32* _pv = (u32*)lcdc_dev->regsbak;
+ _pv += (offset >> 2);
+ (*_pv) |= msk;
+ writel_relaxed(*_pv,lcdc_dev->regs + offset);
+}
+
+static inline void lcdc_clr_bit(struct rk3188_lcdc_device *lcdc_dev,u32 offset,u32 msk)
+{
+ u32* _pv = (u32*)lcdc_dev->regsbak;
+ _pv += (offset >> 2);
+ (*_pv) &= (~msk);
+ writel_relaxed(*_pv,lcdc_dev->regs + offset);
+}
+
+static inline void lcdc_msk_reg(struct rk3188_lcdc_device *lcdc_dev,u32 offset,u32 msk,u32 v)
+{
+ u32 *_pv = (u32*)lcdc_dev->regsbak;
+ _pv += (offset >> 2);
+ (*_pv) &= (~msk);
+ (*_pv) |= v;
+ writel_relaxed(*_pv,lcdc_dev->regs+offset);
+}
+
+static inline void lcdc_cfg_done(struct rk3188_lcdc_device *lcdc_dev)
+{
+ writel_relaxed(0x01,lcdc_dev->regs+REG_CFG_DONE);
+ dsb();
+}
+
+#endif
projects / firefly-linux-kernel-4.4.55.git / commitdiff