ARM STRBT assembly parsing and encoding.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137337 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td
index 9866a2655825a6a5088cce5df39ad2f102972af1..bc5f1b69fd517a1509cfe055e33ee47e8400e0c6 100644 (file)
--- a/lib/Target/ARM/ARMInstrInfo.td
+++ b/lib/Target/ARM/ARMInstrInfo.td
@@ -2350,35 +2350,47 @@ def STRD_POST: AI3stdpo<(outs GPR:$base_wb),
 
 // STRT, STRBT, and STRHT
 
-def STRTr : AI2stridxT<0, 0, (outs GPR:$Rn_wb),
-                     (ins GPR:$Rt, ldst_so_reg:$addr),
-                     IndexModePost, StFrm, IIC_iStore_ru,
-                     "strt", "\t$Rt, $addr", "$addr.base = $Rn_wb",
-                     [/* For disassembly only; pattern left blank */]> {
+def STRBT_POST_REG : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
+                   (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
+                   IndexModePost, StFrm, IIC_iStore_bh_ru,
+                   "strbt", "\t$Rt, $addr, $offset",
+                   "$addr.base = $Rn_wb", []> {
+  // {12}     isAdd
+  // {11-0}   imm12/Rm
+  bits<14> offset;
+  bits<4> addr;
   let Inst{25} = 1;
+  let Inst{23} = offset{12};
   let Inst{21} = 1; // overwrite
+  let Inst{19-16} = addr;
+  let Inst{11-5} = offset{11-5};
   let Inst{4} = 0;
-  let AsmMatchConverter = "cvtStWriteBackRegAddrMode2";
+  let Inst{3-0} = offset{3-0};
   let DecoderMethod = "DecodeAddrMode2IdxInstruction";
 }
 
-def STRTi : AI2stridxT<0, 0, (outs GPR:$Rn_wb),
-                     (ins GPR:$Rt, addrmode_imm12:$addr),
-                     IndexModePost, StFrm, IIC_iStore_ru,
-                     "strt", "\t$Rt, $addr", "$addr.base = $Rn_wb",
-                     [/* For disassembly only; pattern left blank */]> {
+def STRBT_POST_IMM : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
+                   (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
+                   IndexModePost, StFrm, IIC_iStore_bh_ru,
+                   "strbt", "\t$Rt, $addr, $offset",
+                   "$addr.base = $Rn_wb", []> {
+  // {12}     isAdd
+  // {11-0}   imm12/Rm
+  bits<14> offset;
+  bits<4> addr;
   let Inst{25} = 0;
+  let Inst{23} = offset{12};
   let Inst{21} = 1; // overwrite
-  let AsmMatchConverter = "cvtStWriteBackRegAddrMode2";
+  let Inst{19-16} = addr;
+  let Inst{11-0} = offset{11-0};
   let DecoderMethod = "DecodeAddrMode2IdxInstruction";
 }
 
-
-def STRBTr : AI2stridxT<1, 0, (outs GPR:$Rn_wb),
-                      (ins GPR:$Rt, ldst_so_reg:$addr),
-                      IndexModePost, StFrm, IIC_iStore_bh_ru,
-                      "strbt", "\t$Rt, $addr", "$addr.base = $Rn_wb",
-                      [/* For disassembly only; pattern left blank */]> {
+def STRTr : AI2stridxT<0, 0, (outs GPR:$Rn_wb),
+                     (ins GPR:$Rt, ldst_so_reg:$addr),
+                     IndexModePost, StFrm, IIC_iStore_ru,
+                     "strt", "\t$Rt, $addr", "$addr.base = $Rn_wb",
+                     [/* For disassembly only; pattern left blank */]> {
   let Inst{25} = 1;
   let Inst{21} = 1; // overwrite
   let Inst{4} = 0;
@@ -2386,11 +2398,11 @@ def STRBTr : AI2stridxT<1, 0, (outs GPR:$Rn_wb),
   let DecoderMethod = "DecodeAddrMode2IdxInstruction";
 }
 
-def STRBTi : AI2stridxT<1, 0, (outs GPR:$Rn_wb),
-                      (ins GPR:$Rt, addrmode_imm12:$addr),
-                      IndexModePost, StFrm, IIC_iStore_bh_ru,
-                      "strbt", "\t$Rt, $addr", "$addr.base = $Rn_wb",
-                      [/* For disassembly only; pattern left blank */]> {
+def STRTi : AI2stridxT<0, 0, (outs GPR:$Rn_wb),
+                     (ins GPR:$Rt, addrmode_imm12:$addr),
+                     IndexModePost, StFrm, IIC_iStore_ru,
+                     "strt", "\t$Rt, $addr", "$addr.base = $Rn_wb",
+                     [/* For disassembly only; pattern left blank */]> {
   let Inst{25} = 0;
   let Inst{21} = 1; // overwrite
   let AsmMatchConverter = "cvtStWriteBackRegAddrMode2";

diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
index 85e48c7165e74a017d7c574a8b9d033deab9f41b..d5994220a0c202d6ab52e06e23b1a36941e7a696 100644 (file)
--- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
+++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
@@ -939,8 +939,8 @@ static bool DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn,
     case ARM::STR_POST_REG:
     case ARM::STRTr:
     case ARM::STRTi:
-    case ARM::STRBTr:
-    case ARM::STRBTi:
+    case ARM::STRBT_POST_REG:
+    case ARM::STRBT_POST_IMM:
       if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
       break;
     default:

diff --git a/test/MC/ARM/arm-memory-instructions.s b/test/MC/ARM/arm-memory-instructions.s
index fda6031bea4033391d10b13a777b5319954335c3..8af12063e020e358c6995ce4aa90dfb5486cc708 100644 (file)
--- a/test/MC/ARM/arm-memory-instructions.s
+++ b/test/MC/ARM/arm-memory-instructions.s
@@ -375,3 +375,17 @@ _func:
 @ CHECK: strb  r7, [r12, -r3, lsl #5]  @ encoding: [0x83,0x72,0x4c,0xe7]
 @ CHECK: strb  sp, [r7], r2, asr #12   @ encoding: [0x42,0xd6,0xc7,0xe6]
 
+
+@------------------------------------------------------------------------------
+@ STRBT
+@------------------------------------------------------------------------------
+@ FIXME: Optional offset operand.
+        strbt r6, [r2], #12
+        strbt r5, [r6], #-13
+        strbt r4, [r9], r5
+        strbt r3, [r8], -r2, lsl #3
+
+@ CHECK: strbt r6, [r2], #12           @ encoding: [0x0c,0x60,0xe2,0xe4]
+@ CHECK: strbt r5, [r6], #-13          @ encoding: [0x0d,0x50,0x66,0xe4]
+@ CHECK: strbt r4, [r9], r5            @ encoding: [0x05,0x40,0xe9,0xe6]
+@ CHECK: strbt r3, [r8], -r2, lsl #3   @ encoding: [0x82,0x31,0x68,0xe6]