Don't produce ADDC/ADDE when expanding SHL unless they are legal

for the target. This fixes PR3080.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59450 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
index fb05f334c09f3c0d2e6e0dbf4c80ccf45c0d0026..ddc339c324f4aea34a1407d7b32e89bb665778ea 100644 (file)
--- a/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
@@ -1073,7 +1073,8 @@ void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt,
     } else if (Amt == NVTBits) {
       Lo = DAG.getConstant(0, NVT);
       Hi = InL;
-    } else if (Amt == 1) {
+    } else if (Amt == 1 &&
+               TLI.isOperationLegal(ISD::ADDC, TLI.getTypeToExpandTo(NVT))) {
       // Emit this X << 1 as X+X.
       SDVTList VTList = DAG.getVTList(NVT, MVT::Flag);
       SDValue LoOps[2] = { InL, InL };

diff --git a/test/CodeGen/XCore/2008-11-17-Shl64.ll b/test/CodeGen/XCore/2008-11-17-Shl64.ll
new file mode 100644 (file)
index 0000000..97ea41b
--- /dev/null
+++ b/test/CodeGen/XCore/2008-11-17-Shl64.ll
@@ -0,0 +1,6 @@
+; RUN: llvm-as < %s | llc -march=xcore > %t1.s
+; PR3080
+define i64 @test(i64 %a) {
+       %result = shl i64 %a, 1
+       ret i64 %result
+}