}
#ifdef DEBUG
-static void/* inline*/ __sramfunc printch(char byte)
+ void/* inline*/ __sramfunc sram_printch(char byte)
{
unsigned long flags;
u32 gate1, gate2;
cru_writel(gate1, CRU_CLKGATE1_CON);
local_irq_restore(flags);
if (byte == '\n')
- printch('\r');
+ sram_printch('\r');
}
-static void __sramfunc printascii(const char *s)
+ void __sramfunc sram_printascii(const char *s)
{
while (*s) {
if (*s == '\n')
{
- printch('\r');
+ sram_printch('\r');
}
- printch(*s);
+ sram_printch(*s);
s++;
}
}
void print(const char *s)
{
- printascii(s);
+ sram_printascii(s);
}
void __sramfunc print_Hex(unsigned int hex)
{
int i = 8;
- printch('0');
- printch('x');
+ sram_printch('0');
+ sram_printch('x');
while (i--) {
unsigned char c = (hex & 0xF0000000) >> 28;
- printch(c < 0xa ? c + '0' : c - 0xa + 'a');
+ sram_printch(c < 0xa ? c + '0' : c - 0xa + 'a');
hex <<= 4;
}
}
print_Dec(n / 10);
n %= 10;
}
- printch((char)(n + '0'));
+ sram_printch((char)(n + '0'));
}
void print_Dec_3(uint32_t value)
static void /* inline*/ __sramfunc printhex(unsigned int hex)
{
int i = 8;
- printch('0');
- printch('x');
+ sram_printch('0');
+ sram_printch('x');
while (i--) {
unsigned char c = (hex & 0xF0000000) >> 28;
- printch(c < 0xa ? c + '0' : c - 0xa + 'a');
+ sram_printch(c < 0xa ? c + '0' : c - 0xa + 'a');
hex <<= 4;
}
}
#else
-static void inline printch(char byte) {}
-static void inline printascii(const char *s) {}
+static void inline sram_printch(char byte) {}
+static void inline sram_printascii(const char *s) {}
static void inline printhex(unsigned int hex) {}
#endif /* DEBUG */
{
for (;;)
{
- printch(' ');
- printch('8');
- printch('8');
- printch('8');
- printch(' ');
+ sram_printch(' ');
+ sram_printch('8');
+ sram_printch('8');
+ sram_printch('8');
+ sram_printch(' ');
g_crc1 = calc_crc32((u32)_stext, (size_t)(_etext-_stext));
nMHz = 333 + (random32()>>25);
if(nMHz > 402)
nMHz = 402;
printhex(nMHz);
- printch(' ');
+ sram_printch(' ');
printhex(n++);
//ddr_print("%s change freq to: %d MHz\n", __func__, nMHz);
ddr_change_freq(nMHz);
g_crc2 = calc_crc32((u32)_stext, (size_t)(_etext-_stext));
if (g_crc1!=g_crc2)
{
- printch(' ');
- printch('f');
- printch('a');
- printch('i');
- printch('l');
+ sram_printch(' ');
+ sram_printch('f');
+ sram_printch('a');
+ sram_printch('i');
+ sram_printch('l');
}
//ddr_print("check image crc32 success--crc value = 0x%x!, count:%d\n",g_crc1, n++);
- // printascii("change freq success\n");
+ // sram_printascii("change freq success\n");
}
}
else if(ddr_debug == 2)
{
for (;;)
{
- printch(' ');
- printch('9');
- printch('9');
- printch('9');
- printch(' ');
+ sram_printch(' ');
+ sram_printch('9');
+ sram_printch('9');
+ sram_printch('9');
+ sram_printch(' ');
g_crc1 = calc_crc32((u32)_stext, (size_t)(_etext-_stext));
nMHz = (random32()>>13);// 16.7s max
ddr_suspend();
delayus(nMHz);
ddr_resume();
printhex(nMHz);
- printch(' ');
+ sram_printch(' ');
printhex(n++);
g_crc2 = calc_crc32((u32)_stext, (size_t)(_etext-_stext));
if (g_crc1!=g_crc2)
{
- printch(' ');
- printch('f');
- printch('a');
- printch('i');
- printch('l');
+ sram_printch(' ');
+ sram_printch('f');
+ sram_printch('a');
+ sram_printch('i');
+ sram_printch('l');
}
// ddr_print("check image crc32 fail!, count:%d\n", n++);
- // printascii("self refresh fail\n");
+ // sram_printascii("self refresh fail\n");
//else
//ddr_print("check image crc32 success--crc value = 0x%x!, count:%d\n",g_crc1, n++);
- // printascii("self refresh success\n");
+ // sram_printascii("self refresh success\n");
}
}
else if(ddr_debug == 3)
{}
#endif
-void __sramfunc pm_spi_gpio_suspend(void);
-void __sramfunc pm_spi_gpio_resume(void);
-static void __sramfunc rk29_sram_suspend(void)
+void __sramfunc pm_clk_switch_32k(void);
+
+void __sramfunc pm_wfi(void)
{
u32 clksel0;
- u32 vol;
-
- if ((ddr_debug == 1) || (ddr_debug == 2))
- ddr_testmode();
-
- printch('5');
- ddr_suspend();
-
- printch('6');
- vol=rk29_suspend_voltage_set(1000000);
-
- printch('7');
+ sram_printch('7');
clksel0 = cru_readl(CRU_CLKSEL0_CON);
/* set arm clk 24MHz/32 = 750KHz */
cru_writel(clksel0 | 0x1F, CRU_CLKSEL0_CON);
- printch('8');
+ sram_printch('8');
dsb();
asm("wfi");
- printch('8');
+ sram_printch('8');
/* resume arm clk */
cru_writel(clksel0, CRU_CLKSEL0_CON);
- printch('7');
-
+ sram_printch('7');
+
+
+}
+
+static void __sramfunc rk29_sram_suspend(void)
+{
+ u32 vol;
+
+ if ((ddr_debug == 1) || (ddr_debug == 2))
+ ddr_testmode();
+
+ sram_printch('5');
+ ddr_suspend();
+
+ sram_printch('6');
+ vol=rk29_suspend_voltage_set(1000000);
+#ifdef CONFIG_RK29_CLK_SWITCH_TO_32K
+ pm_clk_switch_32k();
+#else
+ pm_wfi();
+#endif
rk29_suspend_voltage_resume(vol);
- printch('6');
+ sram_printch('6');
ddr_resume();
- printch('5');
+ sram_printch('5');
}
static void noinline rk29_suspend(void)
do { \
u32 en = readl(RK29_GPIO##ID##_BASE + GPIO_INTEN); \
if (en) { \
- printascii("GPIO" #ID "_INTEN: "); \
+ sram_printascii("GPIO" #ID "_INTEN: "); \
printhex(en); \
- printch('\n'); \
+ sram_printch('\n'); \
} \
} while (0)
#define DUMP_GPIO_PULL(ID) \
do { \
u32 state = readl(RK29_GRF_BASE + GRF_GPIO0_PULL + (ID<<2)); \
- printascii("GPIO" #ID "_PULL: "); \
+ sram_printascii("GPIO" #ID "_PULL: "); \
printhex(state); \
- printch('\n'); \
+ sram_printch('\n'); \
} while (0)
static void dump_io_pull(void)
DUMP_GPIO_PULL(5);
DUMP_GPIO_PULL(6);
}
+void pm_gpio_suspend(void);
+void pm_gpio_resume(void);
static int rk29_pm_enter(suspend_state_t state)
{
dump_io_pull();
#endif
- printch('0');
+ sram_printch('0');
flush_tlb_all();
interface_ctr_reg_pread();
#endif
) | clkgate[2], CRU_CLKGATE2_CON);
cru_writel(~0, CRU_CLKGATE3_CON);
- printch('1');
+ sram_printch('1');
mode = cru_readl(CRU_MODE_CON);
clksel0 = cru_readl(CRU_CLKSEL0_CON);
delay_500ns();
/* set core = aclk_cpu = hclk_cpu = pclk_cpu = 24MHz */
cru_writel(clksel0 & 0xFFFFF000, CRU_CLKSEL0_CON);
- printch('2');
+ sram_printch('2');
/* suspend codec pll */
cpll = cru_readl(CRU_CPLL_CON);
cru_writel(cpll | PLL_BYPASS, CRU_CPLL_CON);
cru_writel(cpll | PLL_PD | PLL_BYPASS, CRU_CPLL_CON);
delay_500ns();
- printch('3');
+ sram_printch('3');
/* suspend general pll */
gpll = cru_readl(CRU_GPLL_CON);
/* set aclk_periph = hclk_periph = pclk_periph = 24MHz */
cru_writel(clksel0 & ~0x7FC000, CRU_CLKSEL0_CON);
- printch('4');
+ sram_printch('4');
+ pm_gpio_suspend();
rk29_suspend();
- printch('4');
+ pm_gpio_resume();
+ sram_printch('4');
/* resume general pll */
cru_writel(gpll, CRU_GPLL_CON);
/* restore aclk_periph/hclk_periph/pclk_periph */
cru_writel(cru_readl(CRU_CLKSEL0_CON) | (clksel0 & 0x7FC000), CRU_CLKSEL0_CON);
cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_GENERAL_MODE_MASK) | (mode & CRU_GENERAL_MODE_MASK), CRU_MODE_CON);
- printch('3');
+ sram_printch('3');
/* resume codec pll */
cru_writel(cpll, CRU_CPLL_CON);
delay_300us();
cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_CODEC_MODE_MASK) | (mode & CRU_CODEC_MODE_MASK), CRU_MODE_CON);
- printch('2');
+ sram_printch('2');
/* resume arm pll */
cru_writel(apll, CRU_APLL_CON);
/* restore core/aclk_cpu/hclk_cpu/pclk_cpu */
cru_writel(cru_readl(CRU_CLKSEL0_CON) | (clksel0 & 0xFFF), CRU_CLKSEL0_CON);
cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_CPU_MODE_MASK) | (mode & CRU_CPU_MODE_MASK), CRU_MODE_CON);
- printch('1');
+ sram_printch('1');
/* enable clock */
cru_writel(clkgate[0], CRU_CLKGATE0_CON);
cru_writel(clkgate[1], CRU_CLKGATE1_CON);
cru_writel(clkgate[2], CRU_CLKGATE2_CON);
cru_writel(clkgate[3], CRU_CLKGATE3_CON);
- printascii("0\n");
+ sram_printascii("0\n");
dump_irq();
return 0;
-
#include <mach/rk29_iomap.h>
#include <mach/board.h>
#include <mach/sram.h>
#include <mach/iomux.h>
#include <mach/cru.h>
#include <asm/io.h>
-
+#include <mach/gpio.h>
#define SPI_KHZ (1000)
#define SPI_MHZ (1000*1000)
+#define GRF_GPIO0_DIR 0x000
+#define GRF_GPIO1_DIR 0x004
+#define GRF_GPIO2_DIR 0x008
+#define GRF_GPIO3_DIR 0x00c
+#define GRF_GPIO4_DIR 0x010
+#define GRF_GPIO5_DIR 0x014
+
+
+#define GRF_GPIO0_DO 0x018
+#define GRF_GPIO1_DO 0x01c
+#define GRF_GPIO2_DO 0x020
+#define GRF_GPIO3_DO 0x024
+#define GRF_GPIO4_DO 0x028
+#define GRF_GPIO5_DO 0x02c
+
+#define GRF_GPIO0_EN 0x030
+#define GRF_GPIO1_EN 0x034
+#define GRF_GPIO2_EN 0x038
+#define GRF_GPIO3_EN 0x03c
+#define GRF_GPIO4_EN 0x040
+#define GRF_GPIO5_EN 0x044
+
+
+#define GRF_GPIO0L_IOMUX 0x048
+#define GRF_GPIO0H_IOMUX 0x04c
+#define GRF_GPIO1L_IOMUX 0x050
+#define GRF_GPIO1H_IOMUX 0x054
+#define GRF_GPIO2L_IOMUX 0x058
+#define GRF_GPIO2H_IOMUX 0x05c
+#define GRF_GPIO3L_IOMUX 0x060
+#define GRF_GPIO3H_IOMUX 0x064
+#define GRF_GPIO4L_IOMUX 0x068
+#define GRF_GPIO4H_IOMUX 0x06c
+#define GRF_GPIO5L_IOMUX 0x070
+#define GRF_GPIO5H_IOMUX 0x074
//#include <mach/spi_sram.h>
#define SR_RF_EMPT (1 << 3)
#define SR_RF_FULL (1 << 4)
+#define PM_GETGPIO_BASE(N) RK29_GPIO##N##_BASE
+#define PM_GPIO_DR 0
+#define PM_GPIO_DDR 0x4
+#define PM_GPIO_INTEN 0x30
+
+#define wm831x_RD_MSK (0x1<<15)
+#define wm831x_RD_VOID (0x7FFF)
+#define spi_ctr0_mask 0x1fffc3
+
-#define spi_readl(offset) readl(SRAM_SPI_ADDRBASE + offset)
-#define spi_writel(v, offset) writel(v, SRAM_SPI_ADDRBASE + offset)
enum
{
#define sram_spi_cs_dis() spi_writel(spi_readl(SPIM_SER)&~0x3,SPIM_SER)
#define sram_spi_cs_en() spi_writel((spi_readl(SPIM_SER)&~0x3)|(0x1<<SRAM_SPI_CS),SPIM_SER);
#define sram_spi_busy() (spi_readl(SPIM_SR)&SR_BUSY)
+//RK29_PIN0_PA0
+#define pm_gpio_out_low(gpio) pm_gpio_set((gpio),GPIO_OUT,GPIO_LOW)
+#define pm_gpio_out_high(gpio) pm_gpio_set((gpio),GPIO_OUT,GPIO_HIGH)
-#define wm831x_RD_MSK (0x1<<15)
-#define wm831x_RD_VOID (0x7FFF)
-#define spi_ctr0_mask 0x1fffc3
+#define spi_readl(offset) readl(SRAM_SPI_ADDRBASE + offset)
+#define spi_writel(v, offset) writel(v, SRAM_SPI_ADDRBASE + offset)
+
+#define grf_readl(offset) readl(RK29_GRF_BASE + offset)
+#define grf_writel(v, offset) do { writel(v, RK29_GRF_BASE + offset); readl(RK29_GRF_BASE + offset); } while (0)
-#if 0
+#if 1
void __sramfunc sram_printch(char byte);
-void __sramfunc sram_printHX(unsigned int hex);
+#define sram_printHX(a)
#else
#define sram_printch(a)
#define sram_printHX(a)
#define sram_udelay(usecs,a) LOOP((usecs)*LOOPS_PER_USEC)
-#define GRF_GPIO0_DIR 0x000
-#define GRF_GPIO1_DIR 0x004
-#define GRF_GPIO2_DIR 0x008
-#define GRF_GPIO3_DIR 0x00c
-#define GRF_GPIO4_DIR 0x010
-#define GRF_GPIO5_DIR 0x014
-
-
-#define GRF_GPIO0_DO 0x018
-#define GRF_GPIO1_DO 0x01c
-#define GRF_GPIO2_DO 0x020
-#define GRF_GPIO3_DO 0x024
-#define GRF_GPIO4_DO 0x028
-#define GRF_GPIO5_DO 0x02c
-
-#define GRF_GPIO0_EN 0x030
-#define GRF_GPIO1_EN 0x034
-#define GRF_GPIO2_EN 0x038
-#define GRF_GPIO3_EN 0x03c
-#define GRF_GPIO4_EN 0x040
-#define GRF_GPIO5_EN 0x044
-
-
-#define GRF_GPIO0L_IOMUX 0x048
-#define GRF_GPIO0H_IOMUX 0x04c
-#define GRF_GPIO1L_IOMUX 0x050
-#define GRF_GPIO1H_IOMUX 0x054
-#define GRF_GPIO2L_IOMUX 0x058
-#define GRF_GPIO2H_IOMUX 0x05c
-#define GRF_GPIO3L_IOMUX 0x060
-#define GRF_GPIO3H_IOMUX 0x064
-#define GRF_GPIO4L_IOMUX 0x068
-#define GRF_GPIO4H_IOMUX 0x06c
-#define GRF_GPIO5L_IOMUX 0x070
-#define GRF_GPIO5H_IOMUX 0x074
-#define grf_readl(offset) readl(RK29_GRF_BASE + offset)
-#define grf_writel(v, offset) do { writel(v, RK29_GRF_BASE + offset); readl(RK29_GRF_BASE + offset); } while (0)
typedef struct GPIO_IOMUX
{
unsigned int GRF_GPIO_PULL[7];
} GRF_REG_SAVE;
-static GRF_REG_SAVE __sramdata pm_grf;
+__sramdata u32 pm_gpio_base[7]=
+{
+RK29_GPIO0_BASE,
+RK29_GPIO1_BASE,
+RK29_GPIO2_BASE,
+RK29_GPIO3_BASE,
+RK29_GPIO4_BASE,
+RK29_GPIO5_BASE,
+RK29_GPIO6_BASE
+};
+static GRF_REG_SAVE pm_grf;
+int __sramdata crumode;
+
+//static GRF_REG_SAVE __sramdata pm_grf;
-static void __sramfunc pm_spi_gpio_prepare(void)
+static void pm_spi_gpio_prepare(void)
{
pm_grf.GRF_GPIO_IOMUX[1].GPIOL_IOMUX = grf_readl(GRF_GPIO1L_IOMUX);
pm_grf.GRF_GPIO_IOMUX[2].GPIOH_IOMUX = grf_readl(GRF_GPIO2H_IOMUX);
pm_grf.GRF_GPIO_EN[2] = grf_readl(GRF_GPIO2_EN);
}
-static void __sramfunc pm_spi_gpio_suspend(void)
+ void pm_spi_gpio_suspend(void)
{
int io1L_iomux;
int io2H_iomux;
grf_writel(io2_en|0x00ff0000,GRF_GPIO2_EN);
}
-static void __sramfunc pm_spi_gpio_resume(void)
+ void pm_spi_gpio_resume(void)
{
grf_writel(pm_grf.GRF_GPIO_EN[1],GRF_GPIO1_EN);
grf_writel(pm_grf.GRF_GPIO_EN[2],GRF_GPIO2_EN);
grf_writel(pm_grf.GRF_GPIO_IOMUX[2].GPIOH_IOMUX, GRF_GPIO2H_IOMUX);
}
+
+#if defined(CONFIG_RK29_SPI_INSRAM)
+
#define SPI_GATE1_MASK 0xCF
void interface_ctr_reg_pread(void)
writel(temp2,RK29_CRU_BASE + CRU_CLKGATE2_CON);
writel(temp,RK29_CRU_BASE + CRU_CLKGATE1_CON);
+ readl(RK29_GPIO0_BASE);
+ readl(RK29_GPIO1_BASE);
+ readl(RK29_GPIO2_BASE);
+ readl(RK29_GPIO3_BASE);
+ readl(RK29_GPIO4_BASE);
+ readl(RK29_GPIO5_BASE);
+ readl(RK29_GPIO6_BASE);
+
}
spi_data[SPI_CTRLR0] = spi_readl(SPIM_CTRLR0);
spi_data[SPI_BAUDR] = spi_readl(SPIM_BAUDR);
-
spi_writel((spi_data[SPI_CTRLR0]&~0x1fffc3)|0x1<<11|(SRAM_SPI_DATA_BYTE),SPIM_CTRLR0);//spi setting
spi_writel((spi_data[SPI_BAUDR]&(~0xffff))|SRAM_SPI_DIV,SPIM_BAUDR);//setting spi speed
spi_data[SPI_SER]=spi_readl(SPIM_SER);//spi cs
sram_spi_deinit();
#endif
- pm_spi_gpio_suspend();
return 0;
}
unsigned short addr_4003=0x4003;
unsigned short data_4003;
- pm_spi_gpio_resume();
-
sram_spi_init(); //iomux clk
data_4003=sram_spi_read(addr_4003|wm831x_RD_MSK,wm831x_RD_VOID);
sram_printch('G');
data_4003&=~(0x1<<14);
sram_spi_write(addr_4003,data_4003);// sleep
-
-
+
data_4003=sram_spi_read(addr_4003|wm831x_RD_MSK,wm831x_RD_VOID);
sram_printHX(data_4003);//sleep ctr
sram_spi_deinit();
+ sram_udelay(100000, 24);
+
+}
+#endif
+
+
+
+
+void __sramfunc sram_delay_loop(unsigned long count)
+{
+ while (count--) {
+ nop();
+ nop();
+ nop();
+ barrier();
+ }
+}
+
+void __sramfunc pm_gpio_set(unsigned gpio,eGPIOPinDirection_t direction,eGPIOPinLevel_t level)
+{
+ unsigned group,pin,value;
+ group=gpio/32;
+ pin=gpio%32;
+ if(group>6||pin>31)
+ return;
+
+ if(direction==GPIO_OUT)
+ {
+ value=readl(pm_gpio_base[group]+PM_GPIO_DDR);
+ value|=0x1<<pin;
+ writel(value,pm_gpio_base[group]+PM_GPIO_DDR);
+
+ value=readl(pm_gpio_base[group]+PM_GPIO_DR);
+
+ if(level==GPIO_HIGH)
+ value|=0x1<<pin;
+ else
+ value&=~(0x1<<pin);
+
+ writel(value,pm_gpio_base[group]+PM_GPIO_DR);
+
+
+ }
+ else
+ {
+ value=readl(pm_gpio_base[group]+PM_GPIO_DDR);
+ value&=~(0x1<<pin);
+ writel(value,pm_gpio_base[group]+PM_GPIO_DDR);
+
+ }
+}
+/*
+*flag=0,mask
+*/
+
+
+#ifdef CONFIG_RK29_CLK_SWITCH_TO_32K
+
+void __sramfunc pm_clk_switch_32k(void)
+{
+ int vol;
+ sram_printch('7');
+ pm_gpio_out_high(RK29_PIN4_PC0);
+ sram_delay_loop(30);
+
+ crumode=cru_readl(CRU_MODE_CON); //24M to 27M
+ cru_writel((crumode&(~0x7fff))|0x2baa, CRU_MODE_CON);
+ sram_delay_loop(30);
+
+// pm_gpio_iomux(RK29_PIN4_PC5,0x0);// disable 24
+ pm_gpio_out_high(RK29_PIN4_PC5);
+
+ sram_delay_loop(30);
+ dsb();
+ asm("wfi");
- sram_udelay(100000,24);
+ pm_gpio_out_low(RK29_PIN4_PC5);//enable 24M
+ sram_udelay(1000,24);
+ cru_writel(crumode, CRU_MODE_CON); //externel clk 24M
+ pm_gpio_out_low(RK29_PIN4_PC0); //enable 27M
+ sram_udelay(1000,27);
+ sram_printch('7');
+
+
}
+#else
+void __sramfunc pm_clk_switch(void)
+{
+
+}
+#endif
+
+
+
+#ifdef CONFIG_RK29_GPIO_SUSPEND
+void pm_gpio_suspend(void)
+{
+ pm_spi_gpio_suspend(); // spi pullup/pulldown disable.....¡£
+
+}
+
+void pm_gpio_resume(void)
+{
+ pm_spi_gpio_resume(); // spi pullup/pulldown disable.....¡£
+
+}
+
+#else
+void pm_gpio_suspend(void)
+{}
+void pm_gpio_resume(void)
+{}
+#endif
+
+
+
projects / firefly-linux-kernel-4.4.55.git / commitdiff