Fix thinko

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75957 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/SystemZ/SystemZRegisterInfo.td b/lib/Target/SystemZ/SystemZRegisterInfo.td
index bdff54262f9e9b076897e9f428e7aee2dfb22218..4030cfdb41d297bb009abd45811d5f0d6474d19d 100644 (file)
--- a/lib/Target/SystemZ/SystemZRegisterInfo.td
+++ b/lib/Target/SystemZ/SystemZRegisterInfo.td
@@ -119,26 +119,24 @@ def F15 : FPR<15, "f15">, DwarfRegNum<[31]>;
 def PSW : SystemZReg<"psw">;
 
 def subreg_32bit  : PatLeaf<(i32 1)>;
-def subreg_64even : PatLeaf<(i32 2)>;
-def subreg_64odd  : PatLeaf<(i32 3)>;
-def subreg_32even : PatLeaf<(i32 4)>;
-def subreg_32odd  : PatLeaf<(i32 5)>;
+def subreg_even   : PatLeaf<(i32 1)>;
+def subreg_odd    : PatLeaf<(i32 2)>;
 
 def : SubRegSet<1, [R0D, R1D,  R2D,  R3D,  R4D,  R5D,  R6D,  R7D,
                     R8D, R9D, R10D, R11D, R12D, R13D, R14D, R15D],
                    [R0W, R1W,  R2W,  R3W,  R4W,  R5W,  R6W,  R7W,
                     R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W]>;
 
-def : SubRegSet<2, [R0Q, R2Q, R4Q, R6Q, R8Q, R10Q, R12Q, R14Q],
+def : SubRegSet<1, [R0Q, R2Q, R4Q, R6Q, R8Q, R10Q, R12Q, R14Q],
                    [R0D, R2D, R4D, R6D, R8D, R10D, R12D, R14D]>;
 
-def : SubRegSet<3, [R0Q, R2Q, R4Q, R6Q, R8Q, R10Q, R12Q, R14Q],
+def : SubRegSet<2, [R0Q, R2Q, R4Q, R6Q, R8Q, R10Q, R12Q, R14Q],
                    [R1D, R3D, R5D, R7D, R9D, R11D, R13D, R15D]>;
 
-def : SubRegSet<4, [R0P, R2P, R4P, R6P, R8P, R10P, R12P, R14P],
+def : SubRegSet<1, [R0P, R2P, R4P, R6P, R8P, R10P, R12P, R14P],
                    [R0W, R2W, R4W, R6W, R8W, R10W, R12W, R14W]>;
 
-def : SubRegSet<5, [R0P, R2P, R4P, R6P, R8P, R10P, R12P, R14P],
+def : SubRegSet<2, [R0P, R2P, R4P, R6P, R8P, R10P, R12P, R14P],
                    [R1W, R3W, R5W, R7W, R9W, R11W, R13W, R15W]>;
 
 /// Register classes