select CLKSRC_MMIO
select GENERIC_IRQ_CHIP
select HAVE_SCHED_CLOCK
++ + select MULTI_IRQ_HANDLER
help
Support for Freescale MXC/iMX-based family of processors
This workaround defines cpu_relax() as smp_mb(), preventing correctly
written polling loops from denying visibility of updates to memory.
++ config ARM_ERRATA_364296
++ bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
++ depends on CPU_V6 && !SMP
++ help
++ This options enables the workaround for the 364296 ARM1136
++ r0p2 erratum (possible cache data corruption with
++ hit-under-miss enabled). It sets the undocumented bit 31 in
++ the auxiliary control register and the FI bit in the control
++ register, thus disabling hit-under-miss without putting the
++ processor into full low interrupt latency mode. ARM11MPCore
++ is not affected.
++
endmenu
source "arch/arm/common/Kconfig"
.type = CLK_TYPE_PERIPHERAL,
};
+ ++/* HClocks */
+ ++static struct clk hck0 = {
+ ++ .name = "hck0",
+ ++ .pmc_mask = AT91_PMC_HCK0,
+ ++ .type = CLK_TYPE_SYSTEM,
+ ++ .id = 0,
+ ++};
+ ++static struct clk hck1 = {
+ ++ .name = "hck1",
+ ++ .pmc_mask = AT91_PMC_HCK1,
+ ++ .type = CLK_TYPE_SYSTEM,
+ ++ .id = 1,
+ ++};
+ ++
static struct clk *periph_clocks[] __initdata = {
&pioA_clk,
&pioB_clk,
CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
-- CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc1_clk),
++ CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
CLKDEV_CON_DEV_ID("pclk", "ssc.2", &ssc2_clk),
+ ++ CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &hck0),
};
static struct clk_lookup usart_clocks_lookups[] = {
.id = 3,
};
- --/* HClocks */
- --static struct clk hck0 = {
- -- .name = "hck0",
- -- .pmc_mask = AT91_PMC_HCK0,
- -- .type = CLK_TYPE_SYSTEM,
- -- .id = 0,
- --};
- --static struct clk hck1 = {
- -- .name = "hck1",
- -- .pmc_mask = AT91_PMC_HCK1,
- -- .type = CLK_TYPE_SYSTEM,
- -- .id = 1,
- --};
- --
static void __init at91sam9261_register_clocks(void)
{
int i;
.init = eukrea_cpuimx27_timer_init,
};
-- MACHINE_START(CPUIMX27, "EUKREA CPUIMX27")
++ MACHINE_START(EUKREA_CPUIMX27, "EUKREA CPUIMX27")
.boot_params = MX27_PHYS_OFFSET + 0x100,
.map_io = mx27_map_io,
.init_early = imx27_init_early,
.init_irq = mx27_init_irq,
++ + .handle_irq = imx27_handle_irq,
.timer = &eukrea_cpuimx27_timer,
.init_machine = eukrea_cpuimx27_init,
MACHINE_END
I2C_BOARD_INFO("tsc2007", 0x48),
.type = "tsc2007",
.platform_data = &tsc2007_info,
-- - .irq = gpio_to_irq(TSC2007_IRQGPIO),
++ + .irq = IMX_GPIO_TO_IRQ(TSC2007_IRQGPIO),
},
};
.init = eukrea_cpuimx35_timer_init,
};
-- MACHINE_START(EUKREA_CPUIMX35, "Eukrea CPUIMX35")
++ MACHINE_START(EUKREA_CPUIMX35SD, "Eukrea CPUIMX35")
/* Maintainer: Eukrea Electromatique */
.boot_params = MX3x_PHYS_OFFSET + 0x100,
.map_io = mx35_map_io,
.init_early = imx35_init_early,
.init_irq = mx35_init_irq,
++ + .handle_irq = imx35_handle_irq,
.timer = &eukrea_cpuimx35_timer,
.init_machine = eukrea_cpuimx35_init,
MACHINE_END
.init = eukrea_cpuimx25_timer_init,
};
-- MACHINE_START(EUKREA_CPUIMX25, "Eukrea CPUIMX25")
++ MACHINE_START(EUKREA_CPUIMX25SD, "Eukrea CPUIMX25")
/* Maintainer: Eukrea Electromatique */
.boot_params = MX25_PHYS_OFFSET + 0x100,
.map_io = mx25_map_io,
.init_early = imx25_init_early,
.init_irq = mx25_init_irq,
++ + .handle_irq = imx25_handle_irq,
.timer = &eukrea_cpuimx25_timer,
.init_machine = eukrea_cpuimx25_init,
MACHINE_END