{\r
char value;\r
int count, rc = HDMI_ERROR_EDID;\r
- int trytime = 2;\r
+ char hdmi_status = 0;\r
\r
// Config DDC bus clock: ddc_clk = reg_clk/4*(reg 0x4c 0x4b)\r
// when reg00 select reg_clk equal to sys_clk which is equal\r
value |= m_INT_EDID_READY;\r
HDMIWrReg(INTERRUPT_MASK1, value);\r
\r
- \r
- while(trytime--) {\r
- // Reset FIFO offset\r
- HDMIWrReg(EDID_FIFO_OFFSET, 0);\r
- // Set EDID read addr.\r
- HDMIWrReg(EDID_WORD_ADDR, (block%2) * 0x80);\r
- HDMIWrReg(EDID_SEGMENT_POINTER, block/2);\r
- \r
- count = 0;\r
- while(count++ < 10)\r
- { \r
- value = atomic_read(&edid_ready);\r
- if(value)\r
- {\r
- for(count = 0; count < 128; count++)\r
- rk610_hdmi_i2c_read_reg(EDID_FIFO_ADDR, buff + count);\r
- rc = HDMI_ERROR_SUCESS;\r
- break;\r
- }\r
- msleep(100);\r
- }\r
+ // Reset FIFO offset\r
+ HDMIWrReg(EDID_FIFO_OFFSET, 0);\r
+ // Set EDID read addr.\r
+ HDMIWrReg(EDID_WORD_ADDR, (block%2) * 0x80);\r
+ HDMIWrReg(EDID_SEGMENT_POINTER, block/2);\r
+\r
+ count = 0;\r
+ while(count++ < 10)\r
+ { \r
+#ifdef HDMI_USE_IRQ\r
+ value = atomic_read(&edid_ready);\r
+#else \r
+ msleep(10);\r
+ rk610_hdmi_i2c_read_reg(INTERRUPT_STATUS1, &hdmi_status);\r
+ value = (hdmi_status & m_INT_EDID_READY);\r
+#endif\r
+ if(value)\r
+ {\r
+ for(value = 0; value < 128; value++)\r
+ rk610_hdmi_i2c_read_reg(EDID_FIFO_ADDR, buff + value);\r
+ rc = HDMI_ERROR_SUCESS;\r
+ break;\r
+ }\r
+ msleep(100);\r
}\r
// Disable EDID interrupt.\r
value = 0;\r
HDMIWrReg(PHY_PLL_LDO_PWR, v_LDO_PWR_DOWN(1));\r
HDMIWrReg(PHY_BANDGAP_PWR, v_BANDGAP_PWR_DOWN);\r
return 0;\r
-}
\ No newline at end of file
+}\r