begining alpha subtarget support

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23531 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/Alpha/AlphaAsmPrinter.cpp b/lib/Target/Alpha/AlphaAsmPrinter.cpp
index ea5c4690052e569a5b76923f4a7a4ea952233e58..9581c0c532e26b218c7c4d581d12a3bbb480f264 100644 (file)
--- a/lib/Target/Alpha/AlphaAsmPrinter.cpp
+++ b/lib/Target/Alpha/AlphaAsmPrinter.cpp
@@ -14,6 +14,7 @@
 
 #include "Alpha.h"
 #include "AlphaInstrInfo.h"
+#include "AlphaTargetMachine.h"
 #include "llvm/Module.h"
 #include "llvm/Type.h"
 #include "llvm/Assembly/Writer.h"
@@ -29,11 +30,6 @@
 
 using namespace llvm;
 
-namespace llvm {
-  extern cl::opt<bool> EnableAlphaFTOI;
-  extern cl::opt<bool> EnableAlphaCT;
-}
-
 namespace {
   Statistic<> EmittedInsts("asm-printer", "Number of machine instrs printed");
 
@@ -235,7 +231,8 @@ void AlphaAsmPrinter::printConstantPool(MachineConstantPool *MCP) {
 bool AlphaAsmPrinter::doInitialization(Module &M)
 {
   AsmPrinter::doInitialization(M);
-  if(EnableAlphaFTOI || EnableAlphaCT)
+  if(TM.getSubtarget<AlphaSubtarget>().hasF2I() 
+     || TM.getSubtarget<AlphaSubtarget>().hasCT())
     O << "\t.arch ev6\n";
   else
     O << "\t.arch ev56\n";

diff --git a/lib/Target/Alpha/AlphaISelLowering.cpp b/lib/Target/Alpha/AlphaISelLowering.cpp
index 2e5a832e0b033dc5c5e53af8326fcc9b22559892..c6cfc4b9348cfc85a4bc9dc2a5a7abba762e5247 100644 (file)
--- a/lib/Target/Alpha/AlphaISelLowering.cpp
+++ b/lib/Target/Alpha/AlphaISelLowering.cpp
@@ -27,8 +27,6 @@ using namespace llvm;
 
 namespace llvm {
   extern cl::opt<bool> EnableAlphaIDIV;
-  extern cl::opt<bool> EnableAlphaFTOI;
-  extern cl::opt<bool> EnableAlphaCT;
   extern cl::opt<bool> EnableAlphaCount;
   extern cl::opt<bool> EnableAlphaLSMark;
 }
@@ -73,7 +71,7 @@ AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM) : TargetLowering(TM)
   
   setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
   
-  if (!EnableAlphaCT) {
+  if (!TM.getSubtarget<AlphaSubtarget>().hasCT()) {
     setOperationAction(ISD::CTPOP    , MVT::i64  , Expand);
     setOperationAction(ISD::CTTZ     , MVT::i64  , Expand);
     setOperationAction(ISD::CTLZ     , MVT::i64  , Expand);

diff --git a/lib/Target/Alpha/AlphaISelPattern.cpp b/lib/Target/Alpha/AlphaISelPattern.cpp
index c30c459c9041074e461c646a67a14c9d6c517ac9..557da82d1d66f1ad92d943b65a22faedbcfdf7a4 100644 (file)
--- a/lib/Target/Alpha/AlphaISelPattern.cpp
+++ b/lib/Target/Alpha/AlphaISelPattern.cpp
@@ -13,6 +13,7 @@
 
 #include "Alpha.h"
 #include "AlphaRegisterInfo.h"
+#include "AlphaTargetMachine.h"
 #include "AlphaISelLowering.h"
 #include "llvm/Constants.h"                   // FIXME: REMOVE
 #include "llvm/Function.h"
@@ -38,12 +39,6 @@ namespace llvm {
   cl::opt<bool> EnableAlphaIDIV("enable-alpha-intfpdiv",
     cl::desc("Use the FP div instruction for integer div when possible"),
                              cl::Hidden);
-  cl::opt<bool> EnableAlphaFTOI("enable-alpha-FTOI",
-    cl::desc("Enable use of ftoi* and itof* instructions (ev6 and higher)"),
-                             cl::Hidden);
-  cl::opt<bool> EnableAlphaCT("enable-alpha-CT",
-    cl::desc("Enable use of the ctpop, ctlz, and cttz instructions"),
-                              cl::Hidden);
   cl::opt<bool> EnableAlphaCount("enable-alpha-count",
     cl::desc("Print estimates on live ins and outs"),
     cl::Hidden);
@@ -428,7 +423,7 @@ static unsigned GetRelVersion(unsigned opcode)
 void AlphaISel::MoveFP2Int(unsigned src, unsigned dst, bool isDouble)
 {
   unsigned Opc;
-  if (EnableAlphaFTOI) {
+  if (TLI.getTargetMachine().getSubtarget<AlphaSubtarget>().hasF2I()) {
     Opc = isDouble ? Alpha::FTOIT : Alpha::FTOIS;
     BuildMI(BB, Opc, 1, dst).addReg(src).addReg(Alpha::F31);
   } else {
@@ -455,7 +450,7 @@ void AlphaISel::MoveFP2Int(unsigned src, unsigned dst, bool isDouble)
 void AlphaISel::MoveInt2FP(unsigned src, unsigned dst, bool isDouble)
 {
   unsigned Opc;
-  if (EnableAlphaFTOI) {
+  if (TLI.getTargetMachine().getSubtarget<AlphaSubtarget>().hasF2I()) {
     Opc = isDouble?Alpha::ITOFT:Alpha::ITOFS;
     BuildMI(BB, Opc, 1, dst).addReg(src).addReg(Alpha::R31);
   } else {

diff --git a/lib/Target/Alpha/AlphaSubtarget.cpp b/lib/Target/Alpha/AlphaSubtarget.cpp
new file mode 100644 (file)
index 0000000..e1c61d8
--- /dev/null
+++ b/lib/Target/Alpha/AlphaSubtarget.cpp
@@ -0,0 +1,28 @@
+//===- AlphaSubtarget.cpp - Alpha Subtarget Information ---------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file was developed by Andrew Lenharth and is distributed under the
+// University of Illinois Open Source License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements the Alpha specific subclass of TargetSubtarget.
+//
+//===----------------------------------------------------------------------===//
+
+#include "AlphaSubtarget.h"
+#include "Alpha.h"
+#include "llvm/Module.h"
+#include "llvm/Support/CommandLine.h"
+#include "llvm/Target/SubtargetFeature.h"
+
+using namespace llvm;
+
+//"alphaev67-unknown-linux-gnu"
+
+AlphaSubtarget::AlphaSubtarget(const Module &M, const std::string &FS)
+  :HasF2I(false), HasCT(false)
+{
+//TODO: figure out host
+}

diff --git a/lib/Target/Alpha/AlphaSubtarget.h b/lib/Target/Alpha/AlphaSubtarget.h
new file mode 100644 (file)
index 0000000..8eadec0
--- /dev/null
+++ b/lib/Target/Alpha/AlphaSubtarget.h
@@ -0,0 +1,42 @@
+//=====-- AlphaSubtarget.h - Define Subtarget for the Alpha --*- C++ -*--====//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file was developed by Andrew Lenharth and is distributed under the
+// University of Illinois Open Source License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file declares the Alpha specific subclass of TargetSubtarget.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef ALPHASUBTARGET_H
+#define ALPHASUBTARGET_H
+
+#include "llvm/Target/TargetSubtarget.h"
+
+#include <string>
+
+namespace llvm {
+class Module;
+
+class AlphaSubtarget : public TargetSubtarget {
+protected:
+
+  /// Used by the ISel to turn in optimizations for POWER4-derived architectures
+  bool HasF2I;
+  bool HasCT;
+
+public:
+  /// This constructor initializes the data members to match that
+  /// of the specified module.
+  ///
+  AlphaSubtarget(const Module &M, const std::string &FS);
+
+  bool hasF2I() const { return HasF2I; }
+  bool hasCT() const { return HasCT; }
+};
+} // End llvm namespace
+
+#endif

diff --git a/lib/Target/Alpha/AlphaTargetMachine.cpp b/lib/Target/Alpha/AlphaTargetMachine.cpp
index b20cfd36cd6efce48044cbda48fbffc6974eb23e..8f263294052099a5d377bd95b43a2d9b326da2f0 100644 (file)
--- a/lib/Target/Alpha/AlphaTargetMachine.cpp
+++ b/lib/Target/Alpha/AlphaTargetMachine.cpp
@@ -18,6 +18,7 @@
 #include "llvm/Target/TargetOptions.h"
 #include "llvm/Target/TargetMachineRegistry.h"
 #include "llvm/Transforms/Scalar.h"
+#include "llvm/Support/Debug.h"
 #include <iostream>
 
 using namespace llvm;
@@ -62,8 +63,11 @@ AlphaTargetMachine::AlphaTargetMachine(const Module &M, IntrinsicLowering *IL,
                                        const std::string &FS)
   : TargetMachine("alpha", IL, true),
     FrameInfo(TargetFrameInfo::StackGrowsDown, 16, 0),
-    JITInfo(*this)
-{}
+    JITInfo(*this),
+    Subtarget(M, FS)
+{
+  DEBUG(std::cerr << "FS is " << FS << "\n");
+}
 
 /// addPassesToEmitFile - Add passes to the specified pass manager to implement
 /// a static compiler for this target.

diff --git a/lib/Target/Alpha/AlphaTargetMachine.h b/lib/Target/Alpha/AlphaTargetMachine.h
index 4de729acd273edae31b5cf7b5e8b06ea28d16c3a..cc30bba6e3358bdcad12356f0620a99c6a5c31cb 100644 (file)
--- a/lib/Target/Alpha/AlphaTargetMachine.h
+++ b/lib/Target/Alpha/AlphaTargetMachine.h
@@ -19,6 +19,7 @@
 #include "llvm/PassManager.h"
 #include "AlphaInstrInfo.h"
 #include "AlphaJITInfo.h"
+#include "AlphaSubtarget.h"
 
 namespace llvm {
 
@@ -29,6 +30,7 @@ class AlphaTargetMachine : public TargetMachine {
   AlphaInstrInfo InstrInfo;
   TargetFrameInfo FrameInfo;
   AlphaJITInfo JITInfo;
+  AlphaSubtarget Subtarget;
 
 public:
   AlphaTargetMachine(const Module &M, IntrinsicLowering *IL,
@@ -36,6 +38,7 @@ public:
 
   virtual const AlphaInstrInfo *getInstrInfo() const { return &InstrInfo; }
   virtual const TargetFrameInfo  *getFrameInfo() const { return &FrameInfo; }
+  virtual const TargetSubtarget  *getSubtargetImpl() const{ return &Subtarget; }
   virtual const MRegisterInfo *getRegisterInfo() const {
     return &InstrInfo.getRegisterInfo();
   }