/*\r
- * rk29_rt5625.c -- SoC audio for rockchip\r
+ * rk29_rt3261.c -- SoC audio for rockchip\r
*\r
- * Driver for rockchip rt5625 audio\r
+ * Driver for rockchip rt3261 audio\r
*\r
* This program is free software; you can redistribute it and/or modify it\r
* under the terms of the GNU General Public License as published by the\r
ret = snd_soc_dai_set_sysclk(codec_dai, 0, pll_out, SND_SOC_CLOCK_IN);\r
if (ret < 0)\r
{\r
- DBG("rk29_hw_params_rt5625:failed to set the sysclk for codec side\n"); \r
+ DBG("rk29_hw_params_rt3261:failed to set the sysclk for codec side\n"); \r
return ret;\r
}\r
\r
\r
DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__); \r
\r
- /* set codec DAI configuration */\r
- //#if defined (CONFIG_SND_CODEC_SOC_SLAVE) \r
- DBG("Enter::%s----codec slave\n",__FUNCTION__);\r
-\r
- ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_DSP_A |\r
- SND_SOC_DAIFMT_IB_NF | SND_SOC_DAIFMT_CBS_CFS);\r
- /*#endif\r
- //#if defined (CONFIG_SND_CODEC_SOC_MASTER) \r
- DBG("Enter::%s----codec master\n",__FUNCTION__);\r
-\r
ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_DSP_A |\r
SND_SOC_DAIFMT_IB_NF | SND_SOC_DAIFMT_CBM_CFM ); \r
- #endif*/\r
\r
switch(params_rate(params)) {\r
case 8000:\r
break;\r
}\r
\r
- //snd_soc_dai_set_pll(codec_dai, RT5625_PLL_MCLK_TO_VSYSCLK, 0, pll_out, 24576000);???????\r
+ DBG("Enter:%s, %d, rate=%d\n", __FUNCTION__, __LINE__, params_rate(params));\r
\r
/*Set the system clk for codec*/\r
- ret = snd_soc_dai_set_sysclk(codec_dai, 0, 24576000, SND_SOC_CLOCK_IN);\r
+ snd_soc_dai_set_pll(codec_dai, 0, RT3261_PLL1_S_MCLK, pll_out, 256 * 8000);\r
+\r
+ ret = snd_soc_dai_set_sysclk(codec_dai, 0, 256 * 8000, SND_SOC_CLOCK_IN);\r
+\r
\r
if (ret < 0) {\r
- printk("rk29_hw_params_rt5625:failed to set the sysclk for codec side\n"); \r
+ printk("rk29_hw_params_rt3261:failed to set the sysclk for codec side\n"); \r
return ret;\r
}\r
\r
- ret = snd_soc_dai_set_sysclk(cpu_dai, 0, pll_out, 0);\r
+ snd_soc_dai_set_sysclk(cpu_dai, 0, pll_out, 0);\r
+ snd_soc_dai_set_clkdiv(cpu_dai, ROCKCHIP_DIV_BCLK, (pll_out/4)/params_rate(params)-1);\r
+ snd_soc_dai_set_clkdiv(cpu_dai, ROCKCHIP_DIV_MCLK, 3);\r
+\r
+ DBG("Enter:%s, %d, pll_out/4/params_rate(params) = %d \n", __FUNCTION__, __LINE__, (pll_out/4)/params_rate(params));\r
\r
return 0;\r
}\r