lcd b101ew05:add scale timing config for rk610

diff --git a/drivers/video/display/screen/lcd_b101ew05.c b/drivers/video/display/screen/lcd_b101ew05.c
index 70bbdca72f27d49e536e5ad9e8a52fd7374c227c..d3ef5fa43ba7ac97d3fd1282c5768ab0143857e0 100755 (executable)
--- a/drivers/video/display/screen/lcd_b101ew05.c
+++ b/drivers/video/display/screen/lcd_b101ew05.c
@@ -4,6 +4,7 @@
 #include <mach/gpio.h>\r
 #include <mach/iomux.h>\r
 #include <mach/board.h>\r
+#include "../../rockchip/hdmi/rk_hdmi.h"\r
 #include "screen.h"\r
 \r
 #ifdef CONFIG_RK610_LVDS\r
@@ -82,6 +83,208 @@ int dsp_lut[256] ={
                0x00f8f8f8, 0x00f9f9f9, 0x00fafafa, 0x00fbfbfb, 0x00fcfcfc, 0x00fdfdfd, 0x00fefefe, 0x00ffffff, \r
 };\r
 \r
+#ifdef  CONFIG_ONE_LCDC_DUAL_OUTPUT_INF\r
+\r
+/* scaler Timing    */\r
+//1920*1080*60\r
+\r
+#define S_OUT_CLK              SCALE_RATE(148500000,66000000) //m=16 n=9 no=4\r
+#define S_H_PW                 10\r
+#define S_H_BP                 10\r
+#define S_H_VD                 1280\r
+#define S_H_FP                 20\r
+\r
+#define S_V_PW                 10\r
+#define S_V_BP                 10\r
+#define S_V_VD                 800\r
+#define S_V_FP                 13\r
+\r
+#define S_H_ST                 440\r
+#define S_V_ST                 13\r
+\r
+//1920*1080*50\r
+#define S1_OUT_CLK             SCALE_RATE(148500000,57375000)  //m=17 n=11 no=4 \r
+#define S1_H_PW                        10\r
+#define S1_H_BP                        10\r
+#define S1_H_VD                        1280\r
+#define S1_H_FP                        77\r
+\r
+#define S1_V_PW                        10\r
+#define S1_V_BP                        10\r
+#define S1_V_VD                        800\r
+#define S1_V_FP                        13\r
+\r
+#define S1_H_ST                        459\r
+#define S1_V_ST                        13\r
+\r
+//1280*720*60\r
+#define S2_OUT_CLK             SCALE_RATE(74250000,66000000)  //m=32 n=9 no=4\r
+#define S2_H_PW                        10\r
+#define S2_H_BP                        10\r
+#define S2_H_VD                        1280\r
+#define S2_H_FP                        20\r
+\r
+#define S2_V_PW                        10\r
+#define S2_V_BP                        10\r
+#define S2_V_VD                        800\r
+#define S2_V_FP                        13\r
+\r
+#define S2_H_ST                        440\r
+#define S2_V_ST                        13\r
+\r
+//1280*720*50\r
+\r
+#define S3_OUT_CLK             SCALE_RATE(74250000,57375000)   // m=34 n=11 no=4\r
+#define S3_H_PW                        10\r
+#define S3_H_BP                        10\r
+#define S3_H_VD                        1280\r
+#define S3_H_FP                        77\r
+\r
+#define S3_V_PW                        10\r
+#define S3_V_BP                        10\r
+#define S3_V_VD                        800\r
+#define S3_V_FP                        13\r
+\r
+#define S3_H_ST                        459\r
+#define S3_V_ST                        13\r
+\r
+//720*576*50\r
+#define S4_OUT_CLK             SCALE_RATE(27000000,63281250)  //m=75 n=4 no=8\r
+#define S4_H_PW                        10\r
+#define S4_H_BP                        10\r
+#define S4_H_VD                        1280\r
+#define S4_H_FP                        185\r
+\r
+#define S4_V_PW                        10\r
+#define S4_V_BP                        10\r
+#define S4_V_VD                        800\r
+#define S4_V_FP                        48\r
+\r
+#define S4_H_ST                        81\r
+#define S4_V_ST                        48\r
+\r
+//720*480*60\r
+#define S5_OUT_CLK             SCALE_RATE(27000000,75000000)  //m=100 n=9 no=4\r
+#define S5_H_PW                        10\r
+#define S5_H_BP                        10\r
+#define S5_H_VD                        1280\r
+#define S5_H_FP                        130\r
+\r
+#define S5_V_PW                        10\r
+#define S5_V_BP                        10\r
+#define S5_V_VD                        800\r
+#define S5_V_FP                        54\r
+\r
+#define S5_H_ST                        476\r
+#define S5_V_ST                        48\r
+\r
+#define S_DCLK_POL       0\r
+\r
+\r
+static int set_scaler_info(struct rk29fb_screen *screen, u8 hdmi_resolution)\r
+{\r
+    screen->s_clk_inv = S_DCLK_POL;\r
+    screen->s_den_inv = 0;\r
+    screen->s_hv_sync_inv = 0;\r
+    switch(hdmi_resolution){\r
+    case HDMI_1920x1080p_60Hz:\r
+                /* Scaler Timing    */\r
+            screen->hdmi_resolution = hdmi_resolution;\r
+               screen->s_pixclock = S_OUT_CLK;\r
+               screen->s_hsync_len = S_H_PW;\r
+               screen->s_left_margin = S_H_BP;\r
+               screen->s_right_margin = S_H_FP;\r
+               screen->s_hsync_len = S_H_PW;\r
+               screen->s_upper_margin = S_V_BP;\r
+               screen->s_lower_margin = S_V_FP;\r
+               screen->s_vsync_len = S_V_PW;\r
+               screen->s_hsync_st = S_H_ST;\r
+               screen->s_vsync_st = S_V_ST;\r
+               break;\r
+       case HDMI_1920x1080p_50Hz:\r
+                /* Scaler Timing    */\r
+            screen->hdmi_resolution = hdmi_resolution;\r
+               screen->s_pixclock = S1_OUT_CLK;\r
+               screen->s_hsync_len = S1_H_PW;\r
+               screen->s_left_margin = S1_H_BP;\r
+               screen->s_right_margin = S1_H_FP;\r
+               screen->s_hsync_len = S1_H_PW;\r
+               screen->s_upper_margin = S1_V_BP;\r
+               screen->s_lower_margin = S1_V_FP;\r
+               screen->s_vsync_len = S1_V_PW;\r
+               screen->s_hsync_st = S1_H_ST;\r
+               screen->s_vsync_st = S1_V_ST;\r
+               break;\r
+       case HDMI_1280x720p_60Hz:\r
+                /* Scaler Timing    */\r
+            screen->hdmi_resolution = hdmi_resolution;\r
+               screen->s_pixclock = S2_OUT_CLK;\r
+               screen->s_hsync_len = S2_H_PW;\r
+               screen->s_left_margin = S2_H_BP;\r
+               screen->s_right_margin = S2_H_FP;\r
+               screen->s_hsync_len = S2_H_PW;\r
+               screen->s_upper_margin = S2_V_BP;\r
+               screen->s_lower_margin = S2_V_FP;\r
+               screen->s_vsync_len = S2_V_PW;\r
+               screen->s_hsync_st = S2_H_ST;\r
+               screen->s_vsync_st = S2_V_ST;\r
+               break;\r
+    case HDMI_1280x720p_50Hz:\r
+                /* Scaler Timing    */\r
+            screen->hdmi_resolution = hdmi_resolution;\r
+               screen->s_pixclock = S3_OUT_CLK;\r
+               screen->s_hsync_len = S3_H_PW;\r
+               screen->s_left_margin = S3_H_BP;\r
+               screen->s_right_margin = S3_H_FP;\r
+               screen->s_hsync_len = S3_H_PW;\r
+               screen->s_upper_margin = S3_V_BP;\r
+               screen->s_lower_margin = S3_V_FP;\r
+               screen->s_vsync_len = S3_V_PW;\r
+               screen->s_hsync_st = S3_H_ST;\r
+               screen->s_vsync_st = S3_V_ST;\r
+               break;\r
+    case HDMI_720x576p_50Hz_4_3:\r
+    case HDMI_720x576p_50Hz_16_9:\r
+                /* Scaler Timing    */\r
+            screen->hdmi_resolution = hdmi_resolution;\r
+               screen->s_pixclock = S4_OUT_CLK;\r
+               screen->s_hsync_len = S4_H_PW;\r
+               screen->s_left_margin = S4_H_BP;\r
+               screen->s_right_margin = S4_H_FP;\r
+               screen->s_hsync_len = S4_H_PW;\r
+               screen->s_upper_margin = S4_V_BP;\r
+               screen->s_lower_margin = S4_V_FP;\r
+               screen->s_vsync_len = S4_V_PW;\r
+               screen->s_hsync_st = S4_H_ST;\r
+               screen->s_vsync_st = S4_V_ST;\r
+               break;\r
+    case HDMI_720x480p_60Hz_16_9:\r
+    case HDMI_720x480p_60Hz_4_3:\r
+                /* Scaler Timing    */\r
+            screen->hdmi_resolution = hdmi_resolution;\r
+               screen->s_pixclock = S5_OUT_CLK;\r
+               screen->s_hsync_len = S5_H_PW;\r
+               screen->s_left_margin = S5_H_BP;\r
+               screen->s_right_margin = S5_H_FP;\r
+               screen->s_hsync_len = S5_H_PW;\r
+               screen->s_upper_margin = S5_V_BP;\r
+               screen->s_lower_margin = S5_V_FP;\r
+               screen->s_vsync_len = S5_V_PW;\r
+               screen->s_hsync_st = S5_H_ST;\r
+               screen->s_vsync_st = S5_V_ST;\r
+               break;\r
+    default :\r
+            printk("%s lcd not support dual display at this hdmi resolution %d \n",__func__,hdmi_resolution);\r
+            return -1;\r
+               break;\r
+       }\r
+       \r
+       return 0;\r
+}\r
+#else\r
+static int set_scaler_info(struct rk29fb_screen *screen, u8 hdmi_resolution) NULL\r
+#endif\r
+\r
 void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info )\r
 {\r
        /* screen type & face */\r
@@ -123,7 +326,7 @@ void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info )
        screen->init = NULL;\r
        screen->standby = NULL;\r
        screen->dsp_lut = dsp_lut;\r
-       screen->sscreen_get = NULL;//set_scaler_info;\r
+       screen->sscreen_get = set_scaler_info;\r
 #ifdef CONFIG_RK610_LVDS\r
        screen->sscreen_set = rk610_lcd_scaler_set_param;\r
 #endif\r