#define WM8900_REG_CLOCKING1_BCLK_MASK (~0x01e)
#define WM8900_REG_CLOCKING1_OPCLK_MASK (~0x7000)
-#define WM8900_REG_CLOCKING2_ADC_CLKDIV 0xe0
-#define WM8900_REG_CLOCKING2_DAC_CLKDIV 0x1c
+#define WM8900_REG_CLOCKING2_ADC_CLKDIV 0x1c
+#define WM8900_REG_CLOCKING2_DAC_CLKDIV 0xe0
#define WM8900_REG_DACCTRL_MUTE 0x004
#define WM8900_REG_DACCTRL_DAC_SB_FILT 0x100
};
-static const struct snd_kcontrol_new wm8900_dapm_loutput2_control =
-SOC_DAPM_SINGLE("LINEOUT2L Switch", WM8900_REG_POWER3, 6, 1, 0);
+static const struct snd_kcontrol_new wm8900_dapm_loutput2_control[] = {
+SOC_DAPM_SINGLE("LINEOUT2L Switch", WM8900_REG_POWER3, 6, 1, 0),};
-static const struct snd_kcontrol_new wm8900_dapm_routput2_control =
-SOC_DAPM_SINGLE("LINEOUT2R Switch", WM8900_REG_POWER3, 5, 1, 0);
+static const struct snd_kcontrol_new wm8900_dapm_routput2_control[] = {
+SOC_DAPM_SINGLE("LINEOUT2R Switch", WM8900_REG_POWER3, 5, 1, 0),};
static const struct snd_kcontrol_new wm8900_loutmix_controls[] = {
SOC_DAPM_SINGLE("LINPUT3 Bypass Switch", WM8900_REG_LOUTMIXCTL1, 7, 1, 0),
};
static const struct snd_kcontrol_new wm8900_linpga_controls[] = {
-SOC_DAPM_SINGLE("LINPUT1 Switch", WM8900_REG_INCTL, 6, 1, 0),
-SOC_DAPM_SINGLE("LINPUT2 Switch", WM8900_REG_INCTL, 5, 1, 0),
-SOC_DAPM_SINGLE("LINPUT3 Switch", WM8900_REG_INCTL, 4, 1, 0),
+SOC_SINGLE("MIC LINPUT1 Switch", WM8900_REG_INCTL, 6, 1, 0),
+SOC_SINGLE("MIC LINPUT2 Switch", WM8900_REG_INCTL, 5, 1, 0),
+SOC_SINGLE("MIC LINPUT3 Switch", WM8900_REG_INCTL, 4, 1, 0),
};
static const struct snd_kcontrol_new wm8900_rinpga_controls[] = {
-SOC_DAPM_SINGLE("RINPUT1 Switch", WM8900_REG_INCTL, 2, 1, 0),
-SOC_DAPM_SINGLE("RINPUT2 Switch", WM8900_REG_INCTL, 1, 1, 0),
-SOC_DAPM_SINGLE("RINPUT3 Switch", WM8900_REG_INCTL, 0, 1, 0),
+SOC_SINGLE("MIC RINPUT1 Switch", WM8900_REG_INCTL, 2, 1, 0),
+SOC_SINGLE("MIC RINPUT2 Switch", WM8900_REG_INCTL, 1, 1, 0),
+SOC_SINGLE("MIC RINPUT3 Switch", WM8900_REG_INCTL, 0, 1, 0),
+};
+
+static const struct snd_kcontrol_new wm8900_inmix_controls[] = {
+SOC_SINGLE("LINPUT PGA Switch", WM8900_REG_ADCPATH, 6, 1, 0),
+SOC_SINGLE("RINPUT PGA Switch", WM8900_REG_ADCPATH, 2, 1, 0),
};
static const char *wm9700_lp_mux[] = { "Disabled", "Enabled" };
snd_soc_write(codec, WM8900_REG_LOUT2CTL, 0x126);
snd_soc_write(codec, WM8900_REG_ROUT2CTL, 0x126);
snd_soc_write(codec, WM8900_REG_HPCTL1, 0xC0);
+ } else {
+ snd_soc_write(codec, WM8900_REG_POWER1, 0x211D);
+ snd_soc_write(codec, WM8900_REG_POWER2, 0xC03F);
+
+ //User for asound.conf File
+ snd_soc_write(codec, WM8900_REG_LADC_DV, 0x00C1);
+ snd_soc_write(codec, WM8900_REG_RADC_DV, 0x01C0);
+
+ snd_soc_write(codec, WM8900_REG_INCTL, 0x0066);
+
+ snd_soc_write(codec, WM8900_REG_LINVOL, 0x0115);
+ snd_soc_write(codec, WM8900_REG_RINVOL, 0x0115);
+ snd_soc_write(codec, WM8900_REG_INBOOSTMIX1, 0x0042);
+ snd_soc_write(codec, WM8900_REG_INBOOSTMIX2, 0x0042);
+ snd_soc_write(codec, WM8900_REG_ADCPATH, 0x0077);
+
+
+ /*
+ // MIC to DAC
+ snd_soc_write(codec, 0x01, 0x211D);
+ snd_soc_write(codec, 0x02, 0xC03C);
+ snd_soc_write(codec, 0x03, 0x00EC);
+ snd_soc_write(codec, 0x16, 0x0115);
+ snd_soc_write(codec, 0x17, 0x0115);
+ snd_soc_write(codec, 0x1A, 0x0077);
+
+ snd_soc_write(codec, 0x2E, 0x00DD);
+ snd_soc_write(codec, 0x35, 0x011F);
+ snd_soc_write(codec, 0x36, 0x011F);
+ snd_soc_write(codec, 0x3A, 0x00C0);
+ */
}
-
+ WM8900_DBG("<<<<<<<<<<<<<<<<<<<<Exit:%s, %d \n", __FUNCTION__, __LINE__);
return 0;
}
snd_soc_add_controls(codec, wm8900_snd_controls,
ARRAY_SIZE(wm8900_snd_controls));
+ snd_soc_add_controls(codec, wm8900_linpga_controls,
+ ARRAY_SIZE(wm8900_linpga_controls));
+ snd_soc_add_controls(codec, wm8900_rinpga_controls,
+ ARRAY_SIZE(wm8900_rinpga_controls));
+ snd_soc_add_controls(codec, wm8900_inmix_controls,
+ ARRAY_SIZE(wm8900_inmix_controls));
+
wm8900_add_widgets(codec);
ret = snd_soc_init_card(socdev);
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_dai *codec_dai = rtd->dai->codec_dai;
struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
+ unsigned int pll_out = 0;
+ unsigned int lrclk = 0;
int ret;
DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__);
#endif
if (ret < 0)
return ret;
- #if 0
+
/* set cpu DAI configuration */
#if defined (CONFIG_SND_RK29_CODEC_SOC_SLAVE)
ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S |
#endif
if (ret < 0)
return ret;
- #endif
+
}
+
+ switch(params_rate(params)) {
+ case 8000:
+ case 16000:
+ case 24000:
+ case 32000:
+ case 48000:
+ pll_out = 12288000;
+ break;
+ case 11025:
+ case 22050:
+ case 44100:
+ pll_out = 11289600;
+ break;
+ default:
+ DBG("Enter:%s, %d, Error rate=%d\n",__FUNCTION__,__LINE__,params_rate(params));
+ return -EINVAL;
+ break;
+ }
+ DBG("Enter:%s, %d, rate=%d\n",__FUNCTION__,__LINE__,params_rate(params));
+
+ pll_out = 12000000;
+ //snd_soc_dai_set_pll(codec_dai, NULL, 12000000, pll_out);
+
snd_soc_dai_set_clkdiv(codec_dai, WM8900_BCLK_DIV, WM8900_BCLK_DIV_4);
snd_soc_dai_set_clkdiv(codec_dai, WM8900_LRCLK_MODE, 0x400);
- snd_soc_dai_set_clkdiv(codec_dai, WM8900_DAC_LRCLK,0x40);
-
+ snd_soc_dai_set_clkdiv(codec_dai, WM8900_DAC_LRCLK,(pll_out/4)/params_rate(params));
+ snd_soc_dai_set_clkdiv(codec_dai, WM8900_ADC_LRCLK,(pll_out/4)/params_rate(params));
+ DBG("Enter:%s, %d, LRCK=%d\n",__FUNCTION__,__LINE__,(pll_out/4)/params_rate(params));
+
return 0;
}