ARM64: dts: rockchip: add dts file for RK3366 fpga
authorHecanyang <hcy@rock-chips.com>
Fri, 15 Jan 2016 08:38:21 +0000 (16:38 +0800)
committerDavid Wu <david.wu@rock-chips.com>
Mon, 25 Jan 2016 11:07:11 +0000 (19:07 +0800)
Change-Id: I18f6ee0a5a422b05ebb6cf0ac88cfe1076649a91
Signed-off-by: Hecanyang <hcy@rock-chips.com>
Signed-off-by: David Wu <david.wu@rock-chips.com>
arch/arm64/boot/dts/rockchip/rk3366-fpga.dts [new file with mode: 0644]

diff --git a/arch/arm64/boot/dts/rockchip/rk3366-fpga.dts b/arch/arm64/boot/dts/rockchip/rk3366-fpga.dts
new file mode 100644 (file)
index 0000000..278d607
--- /dev/null
@@ -0,0 +1,145 @@
+/*
+ * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This library is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+       model = "rockchip,rk3366-fpga";
+       compatible = "rockchip,rk3366";
+
+       interrupt-parent = <&gic>;
+       #address-cells = <2>;
+       #size-cells = <2>;
+
+       aliases {
+               serial2 = &uart2;
+       };
+
+       chosen {
+               bootargs = "console=uart,mmio32,0xff690000 initrd=0x01FFFFF8,0x00800000";
+       };
+
+       cpus {
+               #address-cells = <2>;
+               #size-cells = <0>;
+
+               cpu0: cpu@0 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a53","arm,armv8";
+                       reg = <0x0 0x0>;
+                       enable-method = "psci";
+               };
+
+               cpu1: cpu@1 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a53","arm,armv8";
+                       reg = <0x0 0x1>;
+                       enable-method = "psci";
+               };
+
+               cpu2: cpu@2 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a53","arm,armv8";
+                       reg = <0x0 0x2>;
+                       enable-method = "psci";
+               };
+
+               cpu3: cpu@3 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a53","arm,armv8";
+                       reg = <0x0 0x3>;
+                       enable-method = "psci";
+               };
+       };
+
+       psci {
+               compatible = "arm,psci";
+               method = "smc";
+       };
+
+       memory@00000000 {
+               device_type = "memory";
+               reg = <0x0 0x00000000 0x0 0x20000000>;
+       };
+
+       timer {
+               compatible = "arm,armv8-timer";
+               interrupts = <
+                               GIC_PPI 13
+                       (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+                               <GIC_PPI 14
+                       (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+                               <GIC_PPI 11
+                       (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+                               <GIC_PPI 10
+                       (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+               clock-frequency = <24000000>;
+       };
+
+       xin24m: xin24m {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <24000000>;
+               clock-output-names = "xin24m";
+       };
+
+       uart2: serial@ff690000 {
+               compatible = "rockchip,rk3366-uart", "snps,dw-apb-uart";
+               reg = <0x0 0xff690000 0x0 0x100>;
+               interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&xin24m>, <&xin24m>;
+               clock-names = "baudclk", "apb_pclk";
+               reg-shift = <2>;
+               reg-io-width = <4>;
+       };
+
+       gic: interrupt-controller@ffb70000 {
+               compatible = "arm,gic-400";
+               #interrupt-cells = <3>;
+               #address-cells = <0>;
+               interrupt-controller;
+               reg = <0x0 0xffb71000 0x0 0x1000>,
+                     <0x0 0xffb72000 0x0 0x1000>;
+       };
+};