at this time, llvm is generating a different but equivalent pattern
that would lead to this instruction. I am trying to think of a way
to get it to generate this. If I can't, I may just remove the pseudo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175419
91177308-0d34-0410-b5e6-
96231b3b80d8
case Mips::BteqzT8SltX16:
ExpandFEXT_T8I816_ins(MBB, MI, Mips::BteqzX16, Mips::SltRxRy16);
break;
+ case Mips::BteqzT8SltuX16:
+ // TBD: figure out a way to get this or remove the instruction
+ // altogether.
+ ExpandFEXT_T8I816_ins(MBB, MI, Mips::BteqzX16, Mips::SltuRxRy16);
+ break;
case Mips::BtnezT8CmpX16:
ExpandFEXT_T8I816_ins(MBB, MI, Mips::BtnezX16, Mips::CmpRxRy16);
break;
// Purpose: Set on Less Than Unsigned
// To record the result of an unsigned less-than comparison.
//
+def SltuRxRy16: FRR16_ins<0b00011, "sltu", IIAlu>;
+
def SltuRxRyRz16: FRRTR16_ins<"sltu"> {
let isCodeGenOnly=1;
}