arm: dts: rockchip: add u2phy1 otg-port node for rk322x SoC

Change-Id: I42efd4227428df38c643c174fb2babcd61064a72
Signed-off-by: William Wu <william.wu@rock-chips.com>

diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi
index e102ec692575994f0ddfbe6188b09fc984e5ad96..3946c8c0697ab6c670b370ad231ccdc0d85226df 100644 (file)
--- a/arch/arm/boot/dts/rk322x.dtsi
+++ b/arch/arm/boot/dts/rk322x.dtsi
@@ -271,6 +271,13 @@
                        clock-output-names = "usb480m_phy1";
                        status = "disabled";
 
+                       u2phy1_otg: otg-port {
+                               #phy-cells = <0>;
+                               interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+                               interrupt-names = "linestate";
+                               status = "disabled";
+                       };
+
                        u2phy1_host: host-port {
                                #phy-cells = <0>;
                                interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
@@ -701,6 +708,8 @@
                reg = <0x30100000 0x20000>;
                interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&cru HCLK_HOST2>, <&u2phy1>;
+               phys = <&u2phy1_otg>;
+               phy-names = "usb";
                clock-names = "usbhost", "utmi";
                status = "disabled";
        };
@@ -711,6 +720,8 @@
                interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&cru HCLK_HOST2>, <&u2phy1>;
                clock-names = "usbhost", "utmi";
+               phys = <&u2phy1_otg>;
+               phy-names = "usb";
                status = "disabled";
        };