gpio0: gpio0@ff750000 {
compatible = "rockchip,rk3288-gpio-bank0";
reg = <0xff750000 0x100>,
- <0xff730080 0x10>,
- <0xff730060 0x0c>,
- <0xff73006c 0x0c>;
+ <0xff730084 0x10>,
+ <0xff730064 0x0c>,
+ <0xff730070 0x0c>;
reg-names = "base", "mux_bank0", "pull_bank0", "drv_bank0";
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_gates17 4>;
case 0:
//pmu
reg = bank->reg_mux_bank0;
- reg += RK3288_GRF_GPIO0_A_IOMUX;
+ //reg += RK3288_GRF_GPIO0_A_IOMUX;
bits = 2;
rk32_iomux_bit_op(bank, pin, mux, reg, bits);
break;
*bit = pin_num % 8;
*bit *= 2;
} else {
- *reg = info->reg_pull;
+ *reg = info->reg_pull - 0x10;
*reg += bank->bank_num * 0x10;
*reg += ((pin_num / 8) * 4);
*bit = pin_num % 8;
*bit *= 2;
} else {
- *reg = info->reg_drv;
+ *reg = info->reg_drv - 0x10;
*reg += bank->bank_num * 0x10;
*reg += ((pin_num / 8) * 4);