clk: rockchip: rk3399: add 65M for PLL freq

VPLL need 65M freq for some HDMI display.

Change-Id: I4f07c97282fb48fc504b54a07838ccb0bbb0355a
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c
index b5a95d87888a197c2927ee15a72e005db4a88c7a..d60fcfea2d566e75b78b117e5fa8d93fce5a8aca 100644 (file)
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -102,6 +102,7 @@ static struct rockchip_pll_rate_table rk3399_pll_rates[] = {
        RK3036_PLL_RATE( 148500000, 1, 99, 4, 4, 1, 0),
        RK3036_PLL_RATE(  96000000, 1, 64, 4, 4, 1, 0),
        RK3036_PLL_RATE(  74250000, 2, 99, 4, 4, 1, 0),
+       RK3036_PLL_RATE(  65000000, 1, 65, 6, 4, 1, 0),
        RK3036_PLL_RATE(  54000000, 1, 54, 6, 4, 1, 0),
        RK3036_PLL_RATE(  27000000, 1, 27, 6, 4, 1, 0),
        { /* sentinel */ },