rk3288: temporarily not limit dclk_lcdc1 div to be even

diff --git a/arch/arm/boot/dts/rk3288-clocks.dtsi b/arch/arm/boot/dts/rk3288-clocks.dtsi
index 986db63a99d429049ab3da29868d62c618a63c47..befc7105424300328061c17fd2c1480d0eb5088c 100755 (executable)
--- a/arch/arm/boot/dts/rk3288-clocks.dtsi
+++ b/arch/arm/boot/dts/rk3288-clocks.dtsi
@@ -1414,7 +1414,7 @@
                                                rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
                                                #clock-cells = <0>;
                                                rockchip,clkops-idx =
-                                                       <CLKOPS_RATE_MUX_EVENDIV>;
+                                                       <CLKOPS_RATE_MUX_DIV>;
                                        };
                                };