staging: comedi: ni_tio: tidy up Gi_DMA_Config_Reg_Bits
authorH Hartley Sweeten <hsweeten@visionengravers.com>
Mon, 28 Jul 2014 17:26:56 +0000 (10:26 -0700)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Wed, 30 Jul 2014 23:51:00 +0000 (16:51 -0700)
Convert this enum into defines and rename the CamelCase symbols.

For aesthetics, move the new defines so they are associated with
the register define.

Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com>
Reviewed-by: Ian Abbott <abbotti@mev.co.uk>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
drivers/staging/comedi/drivers/ni_stc.h
drivers/staging/comedi/drivers/ni_tio_internal.h
drivers/staging/comedi/drivers/ni_tiocmd.c

index caad9d86be8ef0a8c9aef0c5cc3d23577232d366..a2841292ddd49fdd6ed799e07eb626a813d7e117 100644 (file)
@@ -1285,14 +1285,6 @@ static inline unsigned MSeries_PFI_Output_Select_Source(unsigned channel,
        return (bits >> ((channel % 3) * 5)) & 0x1f;
 };
 
-enum MSeries_Gi_DMA_Config_Bits {
-       Gi_DMA_BankSW_Error_Bit = 0x10,
-       Gi_DMA_Reset_Bit = 0x8,
-       Gi_DMA_Int_Enable_Bit = 0x4,
-       Gi_DMA_Write_Bit = 0x2,
-       Gi_DMA_Enable_Bit = 0x1,
-};
-
 static inline unsigned MSeries_PFI_Filter_Select_Mask(unsigned channel)
 {
        return 0x3 << (channel * 2);
index 18a1e16ba0a529a444c1e96303092e4c2d610e97..a74cec40611c9f24b717b48624b5afb60c898573 100644 (file)
 #define GI_HW_SAVE(x)                  (((x) % 2) ? (1 << 13) : (1 << 12))
 #define GI_PERMANENT_STALE(x)          (((x) % 2) ? (1 << 15) : (1 << 14))
 #define NITIO_DMA_CFG_REG(x)           (NITIO_G0_DMA_CFG + (x))
+#define GI_DMA_ENABLE                  (1 << 0)
+#define GI_DMA_WRITE                   (1 << 1)
+#define GI_DMA_INT_ENA                 (1 << 2)
+#define GI_DMA_RESET                   (1 << 3)
+#define GI_DMA_BANKSW_ERROR            (1 << 4)
 #define NITIO_DMA_STATUS_REG(x)                (NITIO_G0_DMA_STATUS + (x))
 #define NITIO_ABZ_REG(x)               (NITIO_G0_ABZ + (x))
 #define NITIO_INT_ACK_REG(x)           (NITIO_G0_INT_ACK + (x))
 #define NITIO_STATUS_REG(x)            (NITIO_G0_STATUS + (x))
 #define NITIO_INT_ENA_REG(x)           (NITIO_G0_INT_ENA + (x))
 
-enum Gi_DMA_Config_Reg_Bits {
-       Gi_DMA_Enable_Bit = 0x1,
-       Gi_DMA_Write_Bit = 0x2,
-       Gi_DMA_Int_Bit = 0x4
-};
-
 enum Gi_DMA_Status_Reg_Bits {
        Gi_DMA_Readbank_Bit = 0x2000,
        Gi_DRQ_Error_Bit = 0x4000,
index 9ba40794ac211830f2978e00cc0ce2adbca03832..d80bb35aed40eb19d61b2b04c41b752a49b99021 100644 (file)
@@ -74,14 +74,14 @@ static void ni_tio_configure_dma(struct ni_gpct *counter, short enable,
                        unsigned gi_dma_config_bits = 0;
 
                        if (enable) {
-                               gi_dma_config_bits |= Gi_DMA_Enable_Bit;
-                               gi_dma_config_bits |= Gi_DMA_Int_Bit;
+                               gi_dma_config_bits |= GI_DMA_ENABLE;
+                               gi_dma_config_bits |= GI_DMA_INT_ENA;
                        }
                        if (read_not_write == 0)
-                               gi_dma_config_bits |= Gi_DMA_Write_Bit;
+                               gi_dma_config_bits |= GI_DMA_WRITE;
                        ni_tio_set_bits(counter, NITIO_DMA_CFG_REG(cidx),
-                                       Gi_DMA_Enable_Bit | Gi_DMA_Int_Bit |
-                                       Gi_DMA_Write_Bit, gi_dma_config_bits);
+                                       GI_DMA_ENABLE | GI_DMA_INT_ENA |
+                                       GI_DMA_WRITE, gi_dma_config_bits);
                }
                break;
        }