SIGN_EXTEND_INREG requires one extra operand, a ValueType node.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35350 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 6187aba6405dad4dd23ff6b616007089e9b40806..8f90521074c6250d66b504c60c873ad06224bdea 100644 (file)
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -2327,8 +2327,12 @@ SDOperand DAGCombiner::ReduceLoadWidth(SDNode *N) {
       CombineTo(N->getOperand(0).Val, Load);
     } else
       CombineTo(N0.Val, Load, Load.getValue(1));
-    if (ShAmt)
-      return DAG.getNode(N->getOpcode(), VT, Load);
+    if (ShAmt) {
+      if (Opc == ISD::SIGN_EXTEND_INREG)
+        return DAG.getNode(Opc, VT, Load, N->getOperand(1));
+      else
+        return DAG.getNode(Opc, VT, Load);
+    }
     return SDOperand(N, 0);   // Return N so it doesn't get rechecked!
   }