Fix a bug in the ARM disassembly of the neon VLD2 all lanes instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152127 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
index 4101f596bf0437eacb4b8f08342f1ca2115bf65e..2d408e77aa44cdb50f9edce16fdd55e93bd3ebad 100644 (file)
--- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
+++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
@@ -2556,17 +2556,14 @@ static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Insn,
   unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
   unsigned align = fieldFromInstruction32(Insn, 4, 1);
   unsigned size = 1 << fieldFromInstruction32(Insn, 6, 2);
-  unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
+  unsigned pred = fieldFromInstruction32(Insn, 22, 4);
   align *= 2*size;
 
   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
     return MCDisassembler::Fail;
-  if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
-    return MCDisassembler::Fail;
-  if (Rm != 0xF) {
-    if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
-      return MCDisassembler::Fail;
-  }
+
+  if (Rm != 0xF)
+    Inst.addOperand(MCOperand::CreateImm(0));
 
   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
     return MCDisassembler::Fail;
@@ -2579,6 +2576,9 @@ static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Insn,
       return MCDisassembler::Fail;
   }
 
+  if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
+    return MCDisassembler::Fail;
+
   return S;
 }
 

diff --git a/test/MC/Disassembler/ARM/neon.txt b/test/MC/Disassembler/ARM/neon.txt
index e4346ec53fa9181efe1f871f5cad0445fbd95b02..609527f7127c0f1d1d6dc5bd2493ea0bbc4117b3 100644 (file)
--- a/test/MC/Disassembler/ARM/neon.txt
+++ b/test/MC/Disassembler/ARM/neon.txt
@@ -1869,3 +1869,10 @@
 # CHECK: vmov.f32      d0, #1.600000e+01
 # CHECK: vmov.f32      q0, #1.600000e+01
 
+# rdar://10798451
+0xe7 0xf9 0x32 0x1d
+# CHECK vld2.8 {d17[], d19[]}, [r7, :16], r2
+0xe7 0xf9 0x3d 0x1d
+# CHECK vld2.8 {d17[], d19[]}, [r7, :16]!
+0xe7 0xf9 0x3f 0x1d
+# CHECK vld2.8 {d17[], d19[]}, [r7, :16]

diff --git a/test/MC/Disassembler/ARM/neont2.txt b/test/MC/Disassembler/ARM/neont2.txt
index ff1838e466e03a3b37bdd5124258ed402c493f09..7da4c89483e6d32ed6a073aece405b83bc95303f 100644 (file)
--- a/test/MC/Disassembler/ARM/neont2.txt
+++ b/test/MC/Disassembler/ARM/neont2.txt
@@ -1588,3 +1588,10 @@
 0x63 0xf9 0x37 0xc9
 # CHECK: vld2.8        {d28, d30}, [r3, :256], r7
 
+# rdar://10798451
+0xe7 0xf9 0x32 0x1d
+# CHECK vld2.8 {d17[], d19[]}, [r7, :16], r2
+0xe7 0xf9 0x3d 0x1d
+# CHECK vld2.8 {d17[], d19[]}, [r7, :16]!
+0xe7 0xf9 0x3f 0x1d
+# CHECK vld2.8 {d17[], d19[]}, [r7, :16]