//static unsigned long lpj_gpll;
-#define PLLS_IN_NORM(pll_id) (((cru_readl(CRU_MODE_CON)&PLL_MODE_MSK(pll_id))\
- ==(PLL_MODE_NORM(pll_id)&PLL_MODE_MSK(pll_id)))\
- &&!(cru_readl(PLL_CONS(pll_id,3))&PLL_BYPASS))
+#define PLLS_IN_NORM(pll_id) (((cru_readl(RK3188_CRU_MODE_CON)&RK3188_PLL_MODE_MSK(pll_id))\
+ ==(RK3188_PLL_MODE_NORM(pll_id)&RK3188_PLL_MODE_MSK(pll_id)))\
+ &&!(cru_readl(RK3188_PLL_CONS(pll_id,3))&RK3188_PLL_BYPASS))
static const struct apll_clk_set apll_table[] = {
// (_mhz, nr, nf, no, _periph_div, _aclk_div)
- _APLL_SET_CLKS(2208, 1, 92, 1, 8, 81),
- _APLL_SET_CLKS(2184, 1, 91, 1, 8, 81),
- _APLL_SET_CLKS(2160, 1, 90, 1, 8, 81),
- _APLL_SET_CLKS(2136, 1, 89, 1, 8, 81),
- _APLL_SET_CLKS(2112, 1, 88, 1, 8, 81),
- _APLL_SET_CLKS(2088, 1, 87, 1, 8, 81),
- _APLL_SET_CLKS(2064, 1, 86, 1, 8, 81),
- _APLL_SET_CLKS(2040, 1, 85, 1, 8, 81),
- _APLL_SET_CLKS(2016, 1, 84, 1, 8, 81),
- _APLL_SET_CLKS(1992, 1, 83, 1, 8, 81),
- _APLL_SET_CLKS(1968, 1, 82, 1, 8, 81),
- _APLL_SET_CLKS(1944, 1, 81, 1, 8, 81),
- _APLL_SET_CLKS(1920, 1, 80, 1, 8, 81),
- _APLL_SET_CLKS(1896, 1, 79, 1, 8, 81),
- _APLL_SET_CLKS(1872, 1, 78, 1, 8, 81),
- _APLL_SET_CLKS(1848, 1, 77, 1, 8, 81),
- _APLL_SET_CLKS(1824, 1, 76, 1, 8, 81),
- _APLL_SET_CLKS(1800, 1, 75, 1, 8, 81),
- _APLL_SET_CLKS(1776, 1, 74, 1, 8, 81),
- _APLL_SET_CLKS(1752, 1, 73, 1, 8, 81),
- _APLL_SET_CLKS(1728, 1, 72, 1, 8, 81),
- _APLL_SET_CLKS(1704, 1, 71, 1, 8, 81),
- _APLL_SET_CLKS(1680, 1, 70, 1, 8, 41),
- _APLL_SET_CLKS(1656, 1, 69, 1, 8, 41),
- _APLL_SET_CLKS(1632, 1, 68, 1, 8, 41),
- _APLL_SET_CLKS(1608, 1, 67, 1, 8, 41),
- _APLL_SET_CLKS(1560, 1, 65, 1, 8, 41),
- _APLL_SET_CLKS(1512, 1, 63, 1, 8, 41),
- _APLL_SET_CLKS(1488, 1, 62, 1, 8, 41),
- _APLL_SET_CLKS(1464, 1, 61, 1, 8, 41),
- _APLL_SET_CLKS(1440, 1, 60, 1, 8, 41),
- _APLL_SET_CLKS(1416, 1, 59, 1, 8, 41),
- _APLL_SET_CLKS(1392, 1, 58, 1, 8, 41),
- _APLL_SET_CLKS(1368, 1, 57, 1, 8, 41),
- _APLL_SET_CLKS(1344, 1, 56, 1, 8, 41),
- _APLL_SET_CLKS(1320, 1, 55, 1, 8, 41),
- _APLL_SET_CLKS(1296, 1, 54, 1, 8, 41),
- _APLL_SET_CLKS(1272, 1, 53, 1, 8, 41),
- _APLL_SET_CLKS(1248, 1, 52, 1, 8, 41),
- _APLL_SET_CLKS(1224, 1, 51, 1, 8, 41),
- _APLL_SET_CLKS(1200, 1, 50, 1, 8, 41),
- _APLL_SET_CLKS(1176, 1, 49, 1, 8, 41),
- _APLL_SET_CLKS(1128, 1, 47, 1, 8, 41),
- _APLL_SET_CLKS(1104, 1, 46, 1, 8, 41),
- _APLL_SET_CLKS(1008, 1, 84, 2, 8, 41),
- _APLL_SET_CLKS(912, 1, 76, 2, 8, 41),
- _APLL_SET_CLKS(888, 1, 74, 2, 8, 41),
- _APLL_SET_CLKS(816, 1, 68, 2, 8, 41),
- _APLL_SET_CLKS(792, 1, 66, 2, 8, 41),
- _APLL_SET_CLKS(696, 1, 58, 2, 8, 41),
- _APLL_SET_CLKS(600, 1, 50, 2, 4, 41),
- _APLL_SET_CLKS(552, 1, 92, 4, 4, 41),
- _APLL_SET_CLKS(504, 1, 84, 4, 4, 41),
- _APLL_SET_CLKS(408, 1, 68, 4, 4, 21),
- _APLL_SET_CLKS(312, 1, 52, 4, 2, 21),
- _APLL_SET_CLKS(252, 1, 84, 8, 2, 21),
- _APLL_SET_CLKS(216, 1, 72, 8, 2, 21),
- _APLL_SET_CLKS(126, 1, 84, 16, 2, 11),
- _APLL_SET_CLKS(48, 1, 32, 16, 2, 11),
- _APLL_SET_CLKS(0, 1, 32, 16, 2, 11),
+ _RK3188_APLL_SET_CLKS(2208, 1, 92, 1, 8, 81),
+ _RK3188_APLL_SET_CLKS(2184, 1, 91, 1, 8, 81),
+ _RK3188_APLL_SET_CLKS(2160, 1, 90, 1, 8, 81),
+ _RK3188_APLL_SET_CLKS(2136, 1, 89, 1, 8, 81),
+ _RK3188_APLL_SET_CLKS(2112, 1, 88, 1, 8, 81),
+ _RK3188_APLL_SET_CLKS(2088, 1, 87, 1, 8, 81),
+ _RK3188_APLL_SET_CLKS(2064, 1, 86, 1, 8, 81),
+ _RK3188_APLL_SET_CLKS(2040, 1, 85, 1, 8, 81),
+ _RK3188_APLL_SET_CLKS(2016, 1, 84, 1, 8, 81),
+ _RK3188_APLL_SET_CLKS(1992, 1, 83, 1, 8, 81),
+ _RK3188_APLL_SET_CLKS(1968, 1, 82, 1, 8, 81),
+ _RK3188_APLL_SET_CLKS(1944, 1, 81, 1, 8, 81),
+ _RK3188_APLL_SET_CLKS(1920, 1, 80, 1, 8, 81),
+ _RK3188_APLL_SET_CLKS(1896, 1, 79, 1, 8, 81),
+ _RK3188_APLL_SET_CLKS(1872, 1, 78, 1, 8, 81),
+ _RK3188_APLL_SET_CLKS(1848, 1, 77, 1, 8, 81),
+ _RK3188_APLL_SET_CLKS(1824, 1, 76, 1, 8, 81),
+ _RK3188_APLL_SET_CLKS(1800, 1, 75, 1, 8, 81),
+ _RK3188_APLL_SET_CLKS(1776, 1, 74, 1, 8, 81),
+ _RK3188_APLL_SET_CLKS(1752, 1, 73, 1, 8, 81),
+ _RK3188_APLL_SET_CLKS(1728, 1, 72, 1, 8, 81),
+ _RK3188_APLL_SET_CLKS(1704, 1, 71, 1, 8, 81),
+ _RK3188_APLL_SET_CLKS(1680, 1, 70, 1, 8, 41),
+ _RK3188_APLL_SET_CLKS(1656, 1, 69, 1, 8, 41),
+ _RK3188_APLL_SET_CLKS(1632, 1, 68, 1, 8, 41),
+ _RK3188_APLL_SET_CLKS(1608, 1, 67, 1, 8, 41),
+ _RK3188_APLL_SET_CLKS(1560, 1, 65, 1, 8, 41),
+ _RK3188_APLL_SET_CLKS(1512, 1, 63, 1, 8, 41),
+ _RK3188_APLL_SET_CLKS(1488, 1, 62, 1, 8, 41),
+ _RK3188_APLL_SET_CLKS(1464, 1, 61, 1, 8, 41),
+ _RK3188_APLL_SET_CLKS(1440, 1, 60, 1, 8, 41),
+ _RK3188_APLL_SET_CLKS(1416, 1, 59, 1, 8, 41),
+ _RK3188_APLL_SET_CLKS(1392, 1, 58, 1, 8, 41),
+ _RK3188_APLL_SET_CLKS(1368, 1, 57, 1, 8, 41),
+ _RK3188_APLL_SET_CLKS(1344, 1, 56, 1, 8, 41),
+ _RK3188_APLL_SET_CLKS(1320, 1, 55, 1, 8, 41),
+ _RK3188_APLL_SET_CLKS(1296, 1, 54, 1, 8, 41),
+ _RK3188_APLL_SET_CLKS(1272, 1, 53, 1, 8, 41),
+ _RK3188_APLL_SET_CLKS(1248, 1, 52, 1, 8, 41),
+ _RK3188_APLL_SET_CLKS(1224, 1, 51, 1, 8, 41),
+ _RK3188_APLL_SET_CLKS(1200, 1, 50, 1, 8, 41),
+ _RK3188_APLL_SET_CLKS(1176, 1, 49, 1, 8, 41),
+ _RK3188_APLL_SET_CLKS(1128, 1, 47, 1, 8, 41),
+ _RK3188_APLL_SET_CLKS(1104, 1, 46, 1, 8, 41),
+ _RK3188_APLL_SET_CLKS(1008, 1, 84, 2, 8, 41),
+ _RK3188_APLL_SET_CLKS(912, 1, 76, 2, 8, 41),
+ _RK3188_APLL_SET_CLKS(888, 1, 74, 2, 8, 41),
+ _RK3188_APLL_SET_CLKS(816, 1, 68, 2, 8, 41),
+ _RK3188_APLL_SET_CLKS(792, 1, 66, 2, 8, 41),
+ _RK3188_APLL_SET_CLKS(696, 1, 58, 2, 8, 41),
+ _RK3188_APLL_SET_CLKS(600, 1, 50, 2, 4, 41),
+ _RK3188_APLL_SET_CLKS(552, 1, 92, 4, 4, 41),
+ _RK3188_APLL_SET_CLKS(504, 1, 84, 4, 4, 41),
+ _RK3188_APLL_SET_CLKS(408, 1, 68, 4, 4, 21),
+ _RK3188_APLL_SET_CLKS(312, 1, 52, 4, 2, 21),
+ _RK3188_APLL_SET_CLKS(252, 1, 84, 8, 2, 21),
+ _RK3188_APLL_SET_CLKS(216, 1, 72, 8, 2, 21),
+ _RK3188_APLL_SET_CLKS(126, 1, 84, 16, 2, 11),
+ _RK3188_APLL_SET_CLKS(48, 1, 32, 16, 2, 11),
+ _RK3188_APLL_SET_CLKS(0, 1, 32, 16, 2, 11),
};
static const struct pll_clk_set pll_com_table[] = {
- _PLL_SET_CLKS(1200000, 1, 50, 1),
- _PLL_SET_CLKS(1188000, 2, 99, 1),
- _PLL_SET_CLKS(891000, 8, 594, 2),
- _PLL_SET_CLKS(768000, 1, 64, 2),
- _PLL_SET_CLKS(594000, 2, 198, 4),
- _PLL_SET_CLKS(408000, 1, 68, 4),
- _PLL_SET_CLKS(384000, 2, 128, 4),
- _PLL_SET_CLKS(360000, 1, 60, 4),
- _PLL_SET_CLKS(300000, 1, 50, 4),
- _PLL_SET_CLKS(297000, 2, 198, 8),
- _PLL_SET_CLKS(148500, 2, 99, 8),
- _PLL_SET_CLKS(0, 0, 0, 0),
+ _RK3188_PLL_SET_CLKS(1200000, 1, 50, 1),
+ _RK3188_PLL_SET_CLKS(1188000, 2, 99, 1),
+ _RK3188_PLL_SET_CLKS(891000, 8, 594, 2),
+ _RK3188_PLL_SET_CLKS(768000, 1, 64, 2),
+ _RK3188_PLL_SET_CLKS(594000, 2, 198, 4),
+ _RK3188_PLL_SET_CLKS(408000, 1, 68, 4),
+ _RK3188_PLL_SET_CLKS(384000, 2, 128, 4),
+ _RK3188_PLL_SET_CLKS(360000, 1, 60, 4),
+ _RK3188_PLL_SET_CLKS(300000, 1, 50, 4),
+ _RK3188_PLL_SET_CLKS(297000, 2, 198, 8),
+ _RK3188_PLL_SET_CLKS(148500, 2, 99, 8),
+ _RK3188_PLL_SET_CLKS(0, 0, 0, 0),
};
static void pll_wait_lock(int pll_idx)
clk_err("PLL_ID=%d\npll_con0=%08x\npll_con1=%08x\n"
"pll_con2=%08x\npll_con3=%08x\n",
pll_idx,
- cru_readl(PLL_CONS(pll_idx, 0)),
- cru_readl(PLL_CONS(pll_idx, 1)),
- cru_readl(PLL_CONS(pll_idx, 2)),
- cru_readl(PLL_CONS(pll_idx, 3)));
+ cru_readl(RK3188_PLL_CONS(pll_idx, 0)),
+ cru_readl(RK3188_PLL_CONS(pll_idx, 1)),
+ cru_readl(RK3188_PLL_CONS(pll_idx, 2)),
+ cru_readl(RK3188_PLL_CONS(pll_idx, 3)));
clk_err("wait pll bit 0x%x time out!\n", bit);
while(1);
unsigned long rate;
if (PLLS_IN_NORM(pll_id)) {
- u32 pll_con0 = cru_readl(PLL_CONS(pll_id, 0));
- u32 pll_con1 = cru_readl(PLL_CONS(pll_id, 1));
+ u32 pll_con0 = cru_readl(RK3188_PLL_CONS(pll_id, 0));
+ u32 pll_con1 = cru_readl(RK3188_PLL_CONS(pll_id, 1));
- u64 rate64 = (u64)parent_rate * PLL_NF(pll_con1);
+ u64 rate64 = (u64)parent_rate * RK3188_PLL_NF(pll_con1);
- do_div(rate64, PLL_NR(pll_con0));
- do_div(rate64, PLL_NO(pll_con0));
+ do_div(rate64, RK3188_PLL_NR(pll_con0));
+ do_div(rate64, RK3188_PLL_NO(pll_con0));
rate = rate64;
} else {
}
switch (pll->id){
- case APLL_ID: {
+ case RK3188_APLL_ID: {
rate_out = clk_apll_round_rate(hw, rate, prate);
break;
}
spin_lock_irqsave(lock, flags);
//enter slowmode
- cru_writel(PLL_MODE_SLOW(pll_id), CRU_MODE_CON);
- cru_writel((0x1<<(16+1))|(0x1<<1), PLL_CONS(pll_id, 3));
+ cru_writel(RK3188_PLL_MODE_SLOW(pll_id), RK3188_CRU_MODE_CON);
+ cru_writel((0x1<<(16+1))|(0x1<<1), RK3188_PLL_CONS(pll_id, 3));
dsb();
dsb();
dsb();
dsb();
dsb();
dsb();
- cru_writel(clk_set->pllcon0, PLL_CONS(pll_id, 0));
- cru_writel(clk_set->pllcon1, PLL_CONS(pll_id, 1));
+ cru_writel(clk_set->pllcon0, RK3188_PLL_CONS(pll_id, 0));
+ cru_writel(clk_set->pllcon1, RK3188_PLL_CONS(pll_id, 1));
- rk30_clock_udelay(1);
+ udelay(1);
- cru_writel((0x1<<(16+1)), PLL_CONS(pll_id, 3));
+ cru_writel((0x1<<(16+1)), RK3188_PLL_CONS(pll_id, 3));
pll_wait_lock(pll_id);
//return from slow
- cru_writel(PLL_MODE_NORM(pll_id), CRU_MODE_CON);
+ cru_writel(RK3188_PLL_MODE_NORM(pll_id), RK3188_CRU_MODE_CON);
if (lock)
spin_unlock_irqrestore(lock, flags);
clk_debug("pll id=%d, dump reg: con0=0x%08x, con1=0x%08x, mode=0x%08x\n",
pll_id,
- cru_readl(PLL_CONS(pll_id,0)),
- cru_readl(PLL_CONS(pll_id,1)),
- cru_readl(CRU_MODE_CON));
+ cru_readl(RK3188_PLL_CONS(pll_id,0)),
+ cru_readl(RK3188_PLL_CONS(pll_id,1)),
+ cru_readl(RK3188_CRU_MODE_CON));
clk_debug("_pll_clk_set_rate end!\n");
if (rate == parent_rate) {
clk_debug("pll id=%d set rate=%lu equal to parent rate\n",
pll->id, rate);
- cru_writel(PLL_MODE_SLOW(pll->id), CRU_MODE_CON);
- cru_writel((0x1 << (16+1)) | (0x1<<1), PLL_CONS(pll->id, 3));
+ cru_writel(RK3188_PLL_MODE_SLOW(pll->id), RK3188_CRU_MODE_CON);
+ cru_writel((0x1 << (16+1)) | (0x1<<1), RK3188_PLL_CONS(pll->id, 3));
clk_debug("pll id=%d enter slow mode, set rate OK!\n", pll->id);
return 0;
}
if (rate == parent_rate) {
clk_debug("pll id=%d set rate=%lu equal to parent rate\n",
pll->id, rate);
- cru_writel(PLL_MODE_SLOW(pll->id), CRU_MODE_CON);
- cru_writel((0x1 << (16+1)) | (0x1<<1), PLL_CONS(pll->id, 3));
+ cru_writel(RK3188_PLL_MODE_SLOW(pll->id), RK3188_CRU_MODE_CON);
+ cru_writel((0x1 << (16+1)) | (0x1<<1), RK3188_PLL_CONS(pll->id, 3));
clk_debug("pll id=%d enter slow mode, set rate OK!\n", pll->id);
return 0;
}
arm_gpll_rate = __clk_get_rate(arm_gpll);
temp_div = DIV_ROUND_UP(arm_gpll_rate, __clk_get_rate(clk));
temp_div = (temp_div == 0) ? 1 : temp_div;
- if (temp_div > CORE_CLK_MAX_DIV) {
+ if (temp_div > RK3188_CORE_CLK_MAX_DIV) {
clk_debug("temp_div %d > max_div %d\n", temp_div,
- CORE_CLK_MAX_DIV);
+ RK3188_CORE_CLK_MAX_DIV);
clk_debug("can't get rate %lu from arm_gpll rate %lu\n",
__clk_get_rate(clk), arm_gpll_rate);
//clk_disable(arm_gpll);
local_irq_save(flags);
/* firstly set div, then select arm_gpll path */
- cru_writel(CORE_CLK_DIV_W_MSK|CORE_CLK_DIV(temp_div), CRU_CLKSELS_CON(0));
- cru_writel(CORE_SEL_PLL_W_MSK|CORE_SEL_GPLL, CRU_CLKSELS_CON(0));
+ cru_writel(RK3188_CORE_CLK_DIV_W_MSK|RK3188_CORE_CLK_DIV(temp_div), RK3188_CRU_CLKSELS_CON(0));
+ cru_writel(RK3188_CORE_SEL_PLL_W_MSK|RK3188_CORE_SEL_GPLL, RK3188_CRU_CLKSELS_CON(0));
sel_gpll = 1;
//loops_per_jiffy = lpj_gpll / temp_div;
*/
//FIXME
//if (!sel_gpll)
- cru_writel(PLL_MODE_SLOW(pll->id), CRU_MODE_CON);
+ cru_writel(RK3188_PLL_MODE_SLOW(pll->id), RK3188_CRU_MODE_CON);
/* PLL power down */
- cru_writel((0x1<<(16+1))|(0x1<<1), PLL_CONS(pll->id, 3));
+ cru_writel((0x1<<(16+1))|(0x1<<1), RK3188_PLL_CONS(pll->id, 3));
dsb();
dsb();
dsb();
dsb();
dsb();
dsb();
- cru_writel(ps->pllcon0, PLL_CONS(pll->id, 0));
- cru_writel(ps->pllcon1, PLL_CONS(pll->id, 1));
+ cru_writel(ps->pllcon0, RK3188_PLL_CONS(pll->id, 0));
+ cru_writel(ps->pllcon1, RK3188_PLL_CONS(pll->id, 1));
- rk30_clock_udelay(1);
+ udelay(1);
/* PLL power up and wait for locked */
- cru_writel((0x1<<(16+1)), PLL_CONS(pll->id, 3));
+ cru_writel((0x1<<(16+1)), RK3188_PLL_CONS(pll->id, 3));
pll_wait_lock(pll->id);
- old_aclk_div = GET_CORE_ACLK_VAL(cru_readl(CRU_CLKSELS_CON(1)) &
- CORE_ACLK_MSK);
- new_aclk_div = GET_CORE_ACLK_VAL(ps->clksel1 & CORE_ACLK_MSK);
+ old_aclk_div = RK3188_GET_CORE_ACLK_VAL(cru_readl(RK3188_CRU_CLKSELS_CON(1)) &
+ RK3188_CORE_ACLK_MSK);
+ new_aclk_div = RK3188_GET_CORE_ACLK_VAL(ps->clksel1 & RK3188_CORE_ACLK_MSK);
if (new_aclk_div >= old_aclk_div) {
- cru_writel(ps->clksel0, CRU_CLKSELS_CON(0));
- cru_writel(ps->clksel1, CRU_CLKSELS_CON(1));
+ cru_writel(ps->clksel0, RK3188_CRU_CLKSELS_CON(0));
+ cru_writel(ps->clksel1, RK3188_CRU_CLKSELS_CON(1));
}
/* PLL return from slow mode */
//FIXME
//if (!sel_gpll)
- cru_writel(PLL_MODE_NORM(pll->id), CRU_MODE_CON);
+ cru_writel(RK3188_PLL_MODE_NORM(pll->id), RK3188_CRU_MODE_CON);
/* reparent to apll, and set div to 1 */
if (sel_gpll) {
- cru_writel(CORE_SEL_PLL_W_MSK|CORE_SEL_APLL, CRU_CLKSELS_CON(0));
- cru_writel(CORE_CLK_DIV_W_MSK|CORE_CLK_DIV(1), CRU_CLKSELS_CON(0));
+ cru_writel(RK3188_CORE_SEL_PLL_W_MSK|RK3188_CORE_SEL_APLL, RK3188_CRU_CLKSELS_CON(0));
+ cru_writel(RK3188_CORE_CLK_DIV_W_MSK|RK3188_CORE_CLK_DIV(1), RK3188_CRU_CLKSELS_CON(0));
}
if (old_aclk_div > new_aclk_div) {
- cru_writel(ps->clksel0, CRU_CLKSELS_CON(0));
- cru_writel(ps->clksel1, CRU_CLKSELS_CON(1));
+ cru_writel(ps->clksel0, RK3188_CRU_CLKSELS_CON(0));
+ cru_writel(ps->clksel1, RK3188_CRU_CLKSELS_CON(1));
}
//loops_per_jiffy = ps->lpj;
clk_debug("apll set rate %lu, con(%x,%x,%x,%x), sel(%x,%x)\n",
ps->rate,
- cru_readl(PLL_CONS(pll->id, 0)),cru_readl(PLL_CONS(pll->id, 1)),
- cru_readl(PLL_CONS(pll->id, 2)),cru_readl(PLL_CONS(pll->id, 3)),
- cru_readl(CRU_CLKSELS_CON(0)),cru_readl(CRU_CLKSELS_CON(1)));
+ cru_readl(RK3188_PLL_CONS(pll->id, 0)),cru_readl(RK3188_PLL_CONS(pll->id, 1)),
+ cru_readl(RK3188_PLL_CONS(pll->id, 2)),cru_readl(RK3188_PLL_CONS(pll->id, 3)),
+ cru_readl(RK3188_CRU_CLKSELS_CON(0)),cru_readl(RK3188_CRU_CLKSELS_CON(1)));
return 0;
}
int ret = 0;
switch (pll->id){
- case APLL_ID: {
+ case RK3188_APLL_ID: {
ret = clk_apll_set_rate(hw, rate, parent_rate);
break;
}
- case DPLL_ID: {
+ case RK3188_DPLL_ID: {
ret = clk_dpll_set_rate(hw, rate, parent_rate);
break;
}
- case GPLL_ID: {
+ case RK3188_GPLL_ID: {
ret = clk_gpll_set_rate(hw, rate, parent_rate);
break;
}
#include <linux/clk-provider.h>
#include <linux/delay.h>
+#include "../../../arch/arm/mach-rockchip/cru.h"
#define CLK_LOOPS_JIFFY_REF (11996091ULL)
#define CLK_LOOPS_RATE_REF (1200UL) //Mhz
#define CLK_LOOPS_RECALC(rate) \
div_u64(CLK_LOOPS_JIFFY_REF*(rate),CLK_LOOPS_RATE_REF*MHZ)
-/*******************cru reg offset***************************/
-#define CRU_MODE_CON 0x40
-#define CRU_CLKSEL_CON 0x44
-#define PLL_CONS(id, i) ((id) * 0x10 + ((i) * 4))
-#define CRU_CLKSELS_CON(i) (CRU_CLKSEL_CON + ((i) * 4))
-
-/*******************cru BITS*********************************/
-#define CRU_GET_REG_BITS_VAL(reg,bits_shift, msk) (((reg) >> (bits_shift))&(msk))
-#define CRU_W_MSK(bits_shift, msk) ((msk) << ((bits_shift) + 16))
-#define CRU_SET_BITS(val,bits_shift, msk) (((val)&(msk)) << (bits_shift))
-#define CRU_W_MSK_SETBITS(val,bits_shift,msk) \
- (CRU_W_MSK(bits_shift, msk)|CRU_SET_BITS(val,bits_shift, msk))
+/*******************RK3188 PLL******************************/
/*******************PLL CON0 BITS***************************/
-#define PLL_CLKFACTOR_SET(val, shift, msk) \
+#define RK3188_PLL_CLKFACTOR_SET(val, shift, msk) \
((((val) - 1) & (msk)) << (shift))
-#define PLL_CLKFACTOR_GET(reg, shift, msk) \
+#define RK3188_PLL_CLKFACTOR_GET(reg, shift, msk) \
((((reg) >> (shift)) & (msk)) + 1)
-#define PLL_OD_MSK (0x3f)
-#define PLL_OD_SHIFT (0x0)
-
-#define PLL_CLKOD(val) PLL_CLKFACTOR_SET(val, PLL_OD_SHIFT, PLL_OD_MSK)
-#define PLL_NO(reg) PLL_CLKFACTOR_GET(reg, PLL_OD_SHIFT, PLL_OD_MSK)
-
-#define PLL_NO_SHIFT(reg) PLL_CLKFACTOR_GET(reg, PLL_OD_SHIFT, PLL_OD_MSK)
+#define RK3188_PLL_OD_MSK (0x3f)
+#define RK3188_PLL_OD_SHIFT (0x0)
+#define RK3188_PLL_CLKOD(val) RK3188_PLL_CLKFACTOR_SET(val, RK3188_PLL_OD_SHIFT, RK3188_PLL_OD_MSK)
+#define RK3188_PLL_NO(reg) RK3188_PLL_CLKFACTOR_GET(reg, RK3188_PLL_OD_SHIFT, RK3188_PLL_OD_MSK)
+#define RK3188_PLL_CLKOD_SET(val) (RK3188_PLL_CLKOD(val) | CRU_W_MSK(RK3188_PLL_OD_SHIFT, RK3188_PLL_OD_MSK))
-#define PLL_CLKOD_SET(val) (PLL_CLKOD(val) | CRU_W_MSK(PLL_OD_SHIFT, PLL_OD_MSK))
+#define RK3188_PLL_NR_MSK (0x3f)
+#define RK3188_PLL_NR_SHIFT (8)
+#define RK3188_PLL_CLKR(val) RK3188_PLL_CLKFACTOR_SET(val, RK3188_PLL_NR_SHIFT, RK3188_PLL_NR_MSK)
+#define RK3188_PLL_NR(reg) RK3188_PLL_CLKFACTOR_GET(reg, RK3188_PLL_NR_SHIFT, RK3188_PLL_NR_MSK)
+#define RK3188_PLL_CLKR_SET(val) (RK3188_PLL_CLKR(val) | CRU_W_MSK(RK3188_PLL_NR_SHIFT, RK3188_PLL_NR_MSK))
-#define PLL_NR_MSK (0x3f)
-#define PLL_NR_SHIFT (8)
-#define PLL_CLKR(val) PLL_CLKFACTOR_SET(val, PLL_NR_SHIFT, PLL_NR_MSK)
-#define PLL_NR(reg) PLL_CLKFACTOR_GET(reg, PLL_NR_SHIFT, PLL_NR_MSK)
+/*FIXME*/
+#define RK3188PLUS_PLL_OD_MSK (0xf)
+#define RK3188PLUS_PLL_NO(reg) (RK3188_PLL_NO(reg) & RK3188PLUS_PLL_OD_MSK)
-#define PLL_CLKR_SET(val) (PLL_CLKR(val) | CRU_W_MSK(PLL_NR_SHIFT, PLL_NR_MSK))
+#define RK3188PLUS_PLL_NR_MSK (0x3f)
+#define RK3188PLUS_PLL_NR(reg) (RK3188_PLL_NR(reg) & RK3188PLUS_PLL_NR_MSK)
-#define PLUS_PLL_OD_MSK (0xf)
-#define PLUS_PLL_NO(reg) (PLL_NO(reg) & PLUS_PLL_OD_MSK)
-
-#define PLUS_PLL_NR_MSK (0x3f)
-#define PLUS_PLL_NR(reg) (PLL_NR(reg) & PLUS_PLL_NR_MSK)
-
-#define PLUS_PLL_CLKR_SET(val) PLL_CLKR_SET(val & PLUS_PLL_NR_MSK)
-#define PLUS_PLL_CLKOD_SET(val) PLL_CLKOD_SET(val & PLUS_PLL_OD_MSK)
+#define RK3188PLUS_PLL_CLKR_SET(val) RK3188_PLL_CLKR_SET(val & RK3188PLUS_PLL_NR_MSK)
+#define RK3188PLUS_PLL_CLKOD_SET(val) RK3188_PLL_CLKOD_SET(val & RK3188PLUS_PLL_OD_MSK)
/*******************PLL CON1 BITS***************************/
-#define PLL_NF_MSK (0xffff)
-#define PLL_NF_SHIFT (0)
-#define PLL_CLKF(val) PLL_CLKFACTOR_SET(val, PLL_NF_SHIFT, PLL_NF_MSK)
-#define PLL_NF(reg) PLL_CLKFACTOR_GET(reg, PLL_NF_SHIFT, PLL_NF_MSK)
-#define PLL_CLKF_SET(val) (PLL_CLKF(val) | CRU_W_MSK(PLL_NF_SHIFT, PLL_NF_MSK))
+#define RK3188_PLL_NF_MSK (0xffff)
+#define RK3188_PLL_NF_SHIFT (0)
+#define RK3188_PLL_CLKF(val) RK3188_PLL_CLKFACTOR_SET(val, RK3188_PLL_NF_SHIFT, RK3188_PLL_NF_MSK)
+#define RK3188_PLL_NF(reg) RK3188_PLL_CLKFACTOR_GET(reg, RK3188_PLL_NF_SHIFT, RK3188_PLL_NF_MSK)
+#define RK3188_PLL_CLKF_SET(val) (RK3188_PLL_CLKF(val) | CRU_W_MSK(RK3188_PLL_NF_SHIFT, RK3188_PLL_NF_MSK))
-#define PLUS_PLL_NF_MSK (0x1fff)
-#define PLUS_PLL_NF(reg) (PLL_NF(reg) & PLUS_PLL_NF_MSK)
-#define PLUS_PLL_CLKF_SET(val) PLL_CLKF_SET(val & PLUS_PLL_NF_MSK)
+#define RK3188PLUS_PLL_NF_MSK (0x1fff)
+#define RK3188PLUS_PLL_NF(reg) (RK3188_PLL_NF(reg) & RK3188PLUS_PLL_NF_MSK)
+#define RK3188PLUS_PLL_CLKF_SET(val) RK3188_PLL_CLKF_SET(val & RK3188PLUS_PLL_NF_MSK)
/*******************PLL CON2 BITS***************************/
-#define PLL_BWADJ_MSK (0xfff)
-#define PLL_BWADJ_SHIFT (0)
-#define PLL_CLK_BWADJ_SET(val) ((val) | CRU_W_MSK(PLL_BWADJ_SHIFT, PLL_BWADJ_MSK))
+#define RK3188_PLL_BWADJ_MSK (0xfff)
+#define RK3188_PLL_BWADJ_SHIFT (0)
+#define RK3188_PLL_CLK_BWADJ_SET(val) ((val) | CRU_W_MSK(RK3188_PLL_BWADJ_SHIFT, RK3188_PLL_BWADJ_MSK))
/*******************PLL CON3 BITS***************************/
-#define PLL_RESET_MSK (1 << 5)
-#define PLL_RESET_W_MSK (PLL_RESET_MSK << 16)
-#define PLL_RESET (1 << 5)
-#define PLL_RESET_RESUME (0 << 5)
-
-#define PLL_BYPASS_MSK (1 << 0)
-#define PLL_BYPASS (1 << 0)
-#define PLL_NO_BYPASS (0 << 0)
-
-#define PLL_PWR_DN_MSK (1 << 1)
-#define PLL_PWR_DN_W_MSK (PLL_PWR_DN_MSK << 16)
-#define PLL_PWR_DN (1 << 1)
-#define PLL_PWR_ON (0 << 1)
-
-#define PLL_STANDBY_MSK (1 << 2)
-#define PLL_STANDBY (1 << 2)
-#define PLL_NO_STANDBY (0 << 2)
-
-/*******************PLL MODE BITS***************************/
-#define PLL_MODE_MSK(id) (0x3 << ((id) * 4))
-#define PLL_MODE_SLOW(id) ((0x0<<((id)*4))|(0x3<<(16+(id)*4)))
-#define PLL_MODE_NORM(id) ((0x1<<((id)*4))|(0x3<<(16+(id)*4)))
-#define PLL_MODE_DEEP(id) ((0x2<<((id)*4))|(0x3<<(16+(id)*4)))
+#define RK3188_PLL_RESET_MSK (1 << 5)
+#define RK3188_PLL_RESET_W_MSK (RK3188_PLL_RESET_MSK << 16)
+#define RK3188_PLL_RESET (1 << 5)
+#define RK3188_PLL_RESET_RESUME (0 << 5)
+
+#define RK3188_PLL_BYPASS_MSK (1 << 0)
+#define RK3188_PLL_BYPASS (1 << 0)
+#define RK3188_PLL_NO_BYPASS (0 << 0)
+
+#define RK3188_PLL_PWR_DN_MSK (1 << 1)
+#define RK3188_PLL_PWR_DN_W_MSK (RK3188_PLL_PWR_DN_MSK << 16)
+#define RK3188_PLL_PWR_DN (1 << 1)
+#define RK3188_PLL_PWR_ON (0 << 1)
+
+#define RK3188_PLL_STANDBY_MSK (1 << 2)
+#define RK3188_PLL_STANDBY (1 << 2)
+#define RK3188_PLL_NO_STANDBY (0 << 2)
/*******************CLKSEL0 BITS***************************/
//core_preiph div
-#define CORE_PERIPH_W_MSK (3 << 22)
-#define CORE_PERIPH_MSK (3 << 6)
-#define CORE_PERIPH_2 (0 << 6)
-#define CORE_PERIPH_4 (1 << 6)
-#define CORE_PERIPH_8 (2 << 6)
-#define CORE_PERIPH_16 (3 << 6)
+#define RK3188_CORE_PERIPH_W_MSK (3 << 22)
+#define RK3188_CORE_PERIPH_MSK (3 << 6)
+#define RK3188_CORE_PERIPH_2 (0 << 6)
+#define RK3188_CORE_PERIPH_4 (1 << 6)
+#define RK3188_CORE_PERIPH_8 (2 << 6)
+#define RK3188_CORE_PERIPH_16 (3 << 6)
//clk_core
-#define CORE_SEL_PLL_MSK (1 << 8)
-#define CORE_SEL_PLL_W_MSK (1 << 24)
-#define CORE_SEL_APLL (0 << 8)
-#define CORE_SEL_GPLL (1 << 8)
+#define RK3188_CORE_SEL_PLL_MSK (1 << 8)
+#define RK3188_CORE_SEL_PLL_W_MSK (1 << 24)
+#define RK3188_CORE_SEL_APLL (0 << 8)
+#define RK3188_CORE_SEL_GPLL (1 << 8)
-#define CORE_CLK_DIV_W_MSK (0x1F << 25)
-#define CORE_CLK_DIV_MSK (0x1F << 9)
-#define CORE_CLK_DIV(i) ((((i) - 1) & 0x1F) << 9)
-#define CORE_CLK_MAX_DIV 32
+#define RK3188_CORE_CLK_DIV_W_MSK (0x1F << 25)
+#define RK3188_CORE_CLK_DIV_MSK (0x1F << 9)
+#define RK3188_CORE_CLK_DIV(i) ((((i) - 1) & 0x1F) << 9)
+#define RK3188_CORE_CLK_MAX_DIV 32
/*******************CLKSEL1 BITS***************************/
//aclk_core div
-#define CORE_ACLK_W_MSK (7 << 19)
-#define CORE_ACLK_MSK (7 << 3)
-#define CORE_ACLK_11 (0 << 3)
-#define CORE_ACLK_21 (1 << 3)
-#define CORE_ACLK_31 (2 << 3)
-#define CORE_ACLK_41 (3 << 3)
-#define CORE_ACLK_81 (4 << 3)
-#define GET_CORE_ACLK_VAL(reg) ((reg)>=4 ? 8:((reg)+1))
+#define RK3188_CORE_ACLK_W_MSK (7 << 19)
+#define RK3188_CORE_ACLK_MSK (7 << 3)
+#define RK3188_CORE_ACLK_11 (0 << 3)
+#define RK3188_CORE_ACLK_21 (1 << 3)
+#define RK3188_CORE_ACLK_31 (2 << 3)
+#define RK3188_CORE_ACLK_41 (3 << 3)
+#define RK3188_CORE_ACLK_81 (4 << 3)
+#define RK3188_GET_CORE_ACLK_VAL(reg) ((reg)>=4 ? 8:((reg)+1))
/*******************PLL SET*********************************/
-#define _PLL_SET_CLKS(_mhz, nr, nf, no) \
+#define _RK3188_PLL_SET_CLKS(_mhz, nr, nf, no) \
{ \
.rate = (_mhz) * KHZ, \
- .pllcon0 = PLL_CLKR_SET(nr)|PLL_CLKOD_SET(no), \
- .pllcon1 = PLL_CLKF_SET(nf),\
- .pllcon2 = PLL_CLK_BWADJ_SET(nf >> 1),\
- .rst_dly=((nr*500)/24+1),\
+ .pllcon0 = RK3188_PLL_CLKR_SET(nr)|RK3188_PLL_CLKOD_SET(no), \
+ .pllcon1 = RK3188_PLL_CLKF_SET(nf),\
+ .pllcon2 = RK3188_PLL_CLK_BWADJ_SET(nf >> 1),\
+ .rst_dly = ((nr*500)/24+1),\
}
-#define _APLL_SET_CLKS(_mhz, nr, nf, no, _periph_div, _aclk_div) \
+#define _RK3188_APLL_SET_CLKS(_mhz, nr, nf, no, _periph_div, _aclk_div) \
{ \
.rate = _mhz * MHZ, \
- .pllcon0 = PLL_CLKR_SET(nr) | PLL_CLKOD_SET(no), \
- .pllcon1 = PLL_CLKF_SET(nf),\
- .pllcon2 = PLL_CLK_BWADJ_SET(nf >> 1),\
- .clksel0 = CORE_PERIPH_W_MSK | CORE_PERIPH_##_periph_div,\
- .clksel1 = CORE_ACLK_W_MSK | CORE_ACLK_##_aclk_div,\
- .lpj= (CLK_LOOPS_JIFFY_REF*_mhz) / CLK_LOOPS_RATE_REF,\
- .rst_dly=((nr*500)/24+1),\
+ .pllcon0 = RK3188_PLL_CLKR_SET(nr) | RK3188_PLL_CLKOD_SET(no), \
+ .pllcon1 = RK3188_PLL_CLKF_SET(nf),\
+ .pllcon2 = RK3188_PLL_CLK_BWADJ_SET(nf >> 1),\
+ .clksel0 = RK3188_CORE_PERIPH_W_MSK | RK3188_CORE_PERIPH_##_periph_div,\
+ .clksel1 = RK3188_CORE_ACLK_W_MSK | RK3188_CORE_ACLK_##_aclk_div,\
+ .lpj = (CLK_LOOPS_JIFFY_REF*_mhz) / CLK_LOOPS_RATE_REF,\
+ .rst_dly = ((nr*500)/24+1),\
}
-/*******************OTHERS*********************************/
-#define rk30_clock_udelay(a) udelay(a)
-
-
-
struct pll_clk_set {
unsigned long rate;
u32 pllcon0;
projects / firefly-linux-kernel-4.4.55.git / commitdiff