Add correct instruction encodings for vbic, vorn, and vmvn.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117282 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMInstrFormats.td b/lib/Target/ARM/ARMInstrFormats.td
index 2e40d0e09a0a33bc5cdc8713899e5c6b0d8c1b12..c10b9acaa146513de79854dad581b401b46efd24 100644 (file)
--- a/lib/Target/ARM/ARMInstrFormats.td
+++ b/lib/Target/ARM/ARMInstrFormats.td
@@ -1698,6 +1698,15 @@ class N2V<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16,
   let Inst{11-7}  = op11_7;
   let Inst{6}     = op6;
   let Inst{4}     = op4;
+  
+  // Instruction operands.
+  bits<5> Vd;
+  bits<5> Vm;
+
+  let Inst{15-12} = Vd{3-0};
+  let Inst{22}    = Vd{4};
+  let Inst{3-0}   = Vm{3-0};
+  let Inst{5}     = Vm{4};
 }
 
 // Same as N2V except it doesn't have a datatype suffix.
@@ -1713,6 +1722,15 @@ class N2VX<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16,
   let Inst{11-7}  = op11_7;
   let Inst{6}     = op6;
   let Inst{4}     = op4;
+  
+  // Instruction operands.
+  bits<5> Vd;
+  bits<5> Vm;
+
+  let Inst{15-12} = Vd{3-0};
+  let Inst{22}    = Vd{4};
+  let Inst{3-0}   = Vm{3-0};
+  let Inst{5}     = Vm{4};
 }
 
 // NEON 2 vector register with immediate.

diff --git a/lib/Target/ARM/ARMInstrNEON.td b/lib/Target/ARM/ARMInstrNEON.td
index 60750edab7d50143c28a0939f1fde5c362872201..417c48b9d5204b6a6a81fe675407c01a3ea5a66c 100644 (file)
--- a/lib/Target/ARM/ARMInstrNEON.td
+++ b/lib/Target/ARM/ARMInstrNEON.td
@@ -2899,19 +2899,22 @@ def  VORNq    : N3VX<0, 0, 0b11, 0b0001, 1, 1, (outs QPR:$dst),
 //   VMVN     : Vector Bitwise NOT (Immediate)
 
 let isReMaterializable = 1 in {
+// FIXME: This instruction's encoding MAY NOT BE correct.
 def VMVNv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 1, 1, (outs DPR:$dst),
                          (ins nModImm:$SIMM), IIC_VMOVImm,
                          "vmvn", "i16", "$dst, $SIMM", "",
                          [(set DPR:$dst, (v4i16 (NEONvmvnImm timm:$SIMM)))]>;
+// FIXME: This instruction's encoding MAY NOT BE correct.
 def VMVNv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 1, 1, (outs QPR:$dst),
                          (ins nModImm:$SIMM), IIC_VMOVImm,
                          "vmvn", "i16", "$dst, $SIMM", "",
                          [(set QPR:$dst, (v8i16 (NEONvmvnImm timm:$SIMM)))]>;
-
+// FIXME: This instruction's encoding MAY NOT BE correct.
 def VMVNv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 1, 1, (outs DPR:$dst),
                          (ins nModImm:$SIMM), IIC_VMOVImm,
                          "vmvn", "i32", "$dst, $SIMM", "",
                          [(set DPR:$dst, (v2i32 (NEONvmvnImm timm:$SIMM)))]>;
+// FIXME: This instruction's encoding MAY NOT BE correct.
 def VMVNv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 1, 1, (outs QPR:$dst),
                          (ins nModImm:$SIMM), IIC_VMOVImm,
                          "vmvn", "i32", "$dst, $SIMM", "",

diff --git a/test/MC/ARM/neon-bitwise-encoding.ll b/test/MC/ARM/neon-bitwise-encoding.ll
index 2a77576867bfd0a26b62490e36eea857bcbf495d..a90d1409265ebeadb5e977691fadd4fcba235380 100644 (file)
--- a/test/MC/ARM/neon-bitwise-encoding.ll
+++ b/test/MC/ARM/neon-bitwise-encoding.ll
@@ -2,6 +2,7 @@
 
 ; FIXME: The following instructions still require testing:
 ;  - vand with immediate
+;  - vmvn of an immediate
 
 ; CHECK: vand_8xi8
 define <8 x i8> @vand_8xi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
@@ -55,4 +56,60 @@ define <16 x i8> @vorr_16xi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 ; CHECK: vorr  q8, q8, q9              @ encoding: [0xf2,0x01,0x60,0xf2]
        %tmp3 = or <16 x i8> %tmp1, %tmp2
        ret <16 x i8> %tmp3
-}
\ No newline at end of file
+}
+
+; CHECK: vbic_8xi8
+define <8 x i8> @vbic_8xi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+       %tmp1 = load <8 x i8>* %A
+       %tmp2 = load <8 x i8>* %B
+; CHECK: vbic  d16, d17, d16           @ encoding: [0xb0,0x01,0x51,0xf2]
+       %tmp3 = xor <8 x i8> %tmp2, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
+       %tmp4 = and <8 x i8> %tmp1, %tmp3
+       ret <8 x i8> %tmp4
+}
+
+; CHECK: vbic_16xi8
+define <16 x i8> @vbic_16xi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+       %tmp1 = load <16 x i8>* %A
+       %tmp2 = load <16 x i8>* %B
+; CHECK: vbic  q8, q8, q9              @ encoding: [0xf2,0x01,0x50,0xf2]
+       %tmp3 = xor <16 x i8> %tmp2, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
+       %tmp4 = and <16 x i8> %tmp1, %tmp3
+       ret <16 x i8> %tmp4
+}
+
+; CHECK: vorn_8xi8
+define <8 x i8> @vorn_8xi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+       %tmp1 = load <8 x i8>* %A
+       %tmp2 = load <8 x i8>* %B
+; CHECK: vorn  d16, d17, d16           @ encoding: [0xb0,0x01,0x71,0xf2]
+       %tmp3 = xor <8 x i8> %tmp2, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
+       %tmp4 = or <8 x i8> %tmp1, %tmp3
+       ret <8 x i8> %tmp4
+}
+
+; CHECK: vorn_16xi8
+define <16 x i8> @vorn_16xi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
+       %tmp1 = load <16 x i8>* %A
+       %tmp2 = load <16 x i8>* %B
+; CHECK: vorn  q8, q8, q9              @ encoding: [0xf2,0x01,0x70,0xf2]
+       %tmp3 = xor <16 x i8> %tmp2, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
+       %tmp4 = or <16 x i8> %tmp1, %tmp3
+       ret <16 x i8> %tmp4
+}
+
+; CHECK: vmvn_8xi8
+define <8 x i8> @vmvn_8xi8(<8 x i8>* %A) nounwind {
+       %tmp1 = load <8 x i8>* %A
+; CHECK: vmvn  d16, d16                @ encoding: [0xa0,0x05,0xf0,0xf3]
+       %tmp2 = xor <8 x i8> %tmp1, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
+       ret <8 x i8> %tmp2
+}
+
+; CHECK: vmvn_16xi8
+define <16 x i8> @vmvn_16xi8(<16 x i8>* %A) nounwind {
+       %tmp1 = load <16 x i8>* %A
+; CHECK: vmvn  q8, q8                  @ encoding: [0xe0,0x05,0xf0,0xf3]
+       %tmp2 = xor <16 x i8> %tmp1, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
+       ret <16 x i8> %tmp2
+}