To use x2apic mode in the CPU's which support x2APIC enhancements or
to support platforms with CPU's having > 8 bit APIC ID, say Y.
+config ROCKCHIP_IOMMU
+ bool "Rockchip IOMMU Support"
+ depends on ARCH_ROCKCHIP
+ select IOMMU_API
+ help
+ Support for the IOMMU(System MMU) of Rockchip rk32xx application
+ processor family. This enables H/W multimedia accellerators to see
+ non-linear physical memory chunks as a linear memory in their
+ address spaces
+
+ If unsure, say N here.
+
+config ROCKCHIP_IOVMM
+ bool "IO Virtual Memory Manager for Rockcihp IOMMUs"
+ select GENERIC_ALLOCATOR
+ depends on ROCKCHIP_IOMMU
+ default n
+ help
+ Supporting the users of Rockchip IOMMU for allocating and mapping
+ an IO virtual memory region with a physical memory region
+ and managing the allocated virtual memory regions.
+
+config ROCKCHIP_IOMMU_DEBUG
+ bool "Debugging log for Rockchip IOMMU"
+ depends on ROCKCHIP_IOMMU
+ help
+ Select this to see the detailed log message that shows what
+ happens in the IOMMU driver
+
+ Say N unless you need kernel log message for IOMMU debugging
+
# OMAP IOMMU support
config OMAP_IOMMU
bool "OMAP IOMMU Support"
obj-$(CONFIG_DMAR_TABLE) += dmar.o
obj-$(CONFIG_INTEL_IOMMU) += iova.o intel-iommu.o
obj-$(CONFIG_IRQ_REMAP) += intel_irq_remapping.o irq_remapping.o
+obj-$(CONFIG_ROCKCHIP_IOVMM) += rockchip-iovmm.o
+obj-$(CONFIG_ROCKCHIP_IOMMU) += rockchip-iommu.o
obj-$(CONFIG_OMAP_IOMMU) += omap-iommu.o
obj-$(CONFIG_OMAP_IOMMU) += omap-iommu2.o
obj-$(CONFIG_OMAP_IOVMM) += omap-iovmm.o
enum rk_sysmmu_inttype itype = SYSMMU_FAULT_UNKNOWN;
u32 status;
u32 rawstat;
+ u32 int_status;
u32 fault_address;
int i, ret = -ENOSYS;
}
else
{
- status = __raw_readl(data->res_bases[i] + SYSMMU_REGISTER_STATUS);
- if(status != 0)
+ int_status = __raw_readl(data->res_bases[i] + SYSMMU_REGISTER_INT_STATUS);
+ if(int_status != 0)
{
+ /*mask status*/
+ __raw_writel(0x00,data->res_bases[i] + SYSMMU_REGISTER_INT_MASK);
+
rawstat = __raw_readl(data->res_bases[i] + SYSMMU_REGISTER_INT_RAWSTAT);
if(rawstat & SYSMMU_INTERRUPT_PAGE_FAULT)
{
goto out;
}
}
+ else
+ goto out;
}
if (data->domain)
unsigned long base = data->pgtable;
if (itype != SYSMMU_FAULT_UNKNOWN)
base = __raw_readl(data->res_bases[i] + SYSMMU_REGISTER_DTE_ADDR);
+ status = __raw_readl(data->res_bases[i] + SYSMMU_REGISTER_STATUS);
ret = data->fault_handler(data->dev, itype, base, fault_address,status);
}
if (!ret && (itype != SYSMMU_FAULT_UNKNOWN))
{
if(SYSMMU_PAGEFAULT == itype)
+ {
+ sysmmu_zap_tlb(data->res_bases[i]);
sysmmu_page_fault_done(data->res_bases[i],data->dbgname);
+ }
sysmmu_reset(data->res_bases[i],data->dbgname);
}
else
struct rk_iovmm *vmm = rockchip_get_iovmm(dev);
int order;
int ret;
-
+
for (; sg_dma_len(sg) < offset; sg = sg_next(sg))
offset -= sg_dma_len(sg);
spin_unlock(&vmm->lock);
+ rockchip_sysmmu_tlb_invalidate(dev);
+
dev_dbg(dev, "IOVMM: Allocated VM region @ %#x/%#X bytes.\n",region->start, region->size);
return region->start;
list_add(®ion->node, &vmm->regions_list);
spin_unlock(&vmm->lock);
+
+ rockchip_sysmmu_tlb_invalidate(dev);
return 0;
}