ARM64: dts: rockchip: rk3366: add initial clock rate for plls

Change-Id: I9ea6bcac10a7b67471613aea3ea41aff44a8fe34
Signed-off-by: Feng Xiao <xf@rock-chips.com>

diff --git a/arch/arm64/boot/dts/rockchip/rk3366.dtsi b/arch/arm64/boot/dts/rockchip/rk3366.dtsi
index 734aa7d1300a8966a4d7e5e2ce2da15703d072ca..23e2134ec23782b51618b63b7d01678f57a60449 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3366.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3366.dtsi
@@ -545,6 +545,14 @@
                rockchip,grf = <&grf>;
                #clock-cells = <1>;
                #reset-cells = <1>;
+               assigned-clocks =
+                       <&cru PLL_CPLL>, <&cru PLL_GPLL>,
+                       <&cru PLL_NPLL>, <&cru PLL_MPLL>,
+                       <&cru PLL_WPLL>, <&cru PLL_BPLL>;
+               assigned-clock-rates =
+                       <750000000>, <576000000>,
+                       <594000000>, <594000000>,
+                       <480000000>, <520000000>;
        };
 
        grf: syscon@ff770000 {