work-in-progress

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118358 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td
index 18ea78a00ed71cc8059bf8f49acf7e1e3bf9a591..05adb4d9dba29700446c5f4061be4f9401c95cbd 100644 (file)
--- a/lib/Target/X86/X86InstrInfo.td
+++ b/lib/Target/X86/X86InstrInfo.td
@@ -1504,9 +1504,9 @@ def : InstAlias<"outl $port", (OUT32ir i8imm:$port)>;
 // errors, since its encoding is the most compact.
 def : InstAlias<"sldt $mem", (SLDT16m i16mem:$mem)>;
 
-// "rc[lr] X" is an alias for "rcl X, 1"
 /*
-multiclass RotateAlias<string Mnemonic, string Opc> {
+// "shl X, $1" is an alias for "shl X".
+multiclass ShiftRotateByOneAlias<string Mnemonic, string Opc> {
  def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"),
                  (!cast<Instruction>(!strconcat(Opc, "8r1")) GR8:$op)>;
  def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"),
@@ -1525,13 +1525,12 @@ multiclass RotateAlias<string Mnemonic, string Opc> {
                  (!cast<Instruction>(!strconcat(Opc, "64m1")) i64mem:$op)>;
 }
 
-defm : RotateAlias<"rcl", "RCL">;
-defm : RotateAlias<"rcr", "RCR">;
-defm : RotateAlias<"rol", "ROL">;
-defm : RotateAlias<"ror", "ROR">;
+defm : ShiftRotateByOneAlias<"rcl", "RCL">;
+defm : ShiftRotateByOneAlias<"rcr", "RCR">;
+defm : ShiftRotateByOneAlias<"rol", "ROL">;
+defm : ShiftRotateByOneAlias<"ror", "ROR">;
 */
 
-
 // test: We accept "testX <reg>, <mem>" and "testX <mem>, <reg>" as synonyms.
 def : InstAlias<"testb $val, $mem", (TEST8rm  GR8 :$val, i8mem :$mem)>;
 def : InstAlias<"testw $val, $mem", (TEST16rm GR16:$val, i16mem:$mem)>;