ARM: bL boot on A7 cluster

Ensure that A7 cluster will be mapped on CPU0-2

Suggested-by: Chris Redpath <Chris.Redpath@arm.com>
Signed-off-by: Vincent Guittot <vincent.guittot@linaro.org>

diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
index 446708869c7a257b07064c3c7e212804eee82008..f6b4e8471cb682e81ed3ba59035314f0dc46deaf 100644 (file)
--- a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
@@ -75,24 +75,6 @@
                #address-cells = <1>;
                #size-cells = <0>;
 
-               cpu0: cpu@0 {
-                       device_type = "cpu";
-                       compatible = "arm,cortex-a15";
-                       reg = <0>;
-                       cluster = <&cluster0>;
-                       core = <&core0>;
-                       clock-frequency = <1000000000>;
-               };
-
-               cpu1: cpu@1 {
-                       device_type = "cpu";
-                       compatible = "arm,cortex-a15";
-                       reg = <1>;
-                       cluster = <&cluster0>;
-                       core = <&core1>;
-                       clock-frequency = <1000000000>;
-               };
-
                cpu2: cpu@2 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a7";
@@ -119,6 +101,25 @@
                        core = <&core4>;
                        clock-frequency = <800000000>;
                };
+
+               cpu0: cpu@0 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a15";
+                       reg = <0>;
+                       cluster = <&cluster0>;
+                       core = <&core0>;
+                       clock-frequency = <1000000000>;
+               };
+
+               cpu1: cpu@1 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a15";
+                       reg = <1>;
+                       cluster = <&cluster0>;
+                       core = <&core1>;
+                       clock-frequency = <1000000000>;
+               };
+
        };
 
        memory@80000000 {