namespace llvm {
-class MCSectionData;
class MachObjectWriter;
class MCMachObjectTargetWriter {
: Sym(Sym), MRE(MRE) {}
};
- llvm::DenseMap<const MCSectionData *, std::vector<RelAndSymbol>> Relocations;
- llvm::DenseMap<const MCSectionData*, unsigned> IndirectSymBase;
+ llvm::DenseMap<const MCSection *, std::vector<RelAndSymbol>> Relocations;
+ llvm::DenseMap<const MCSection *, unsigned> IndirectSymBase;
/// @}
/// \name Symbol Table Data
uint64_t getFragmentAddress(const MCFragment *Fragment,
const MCAsmLayout &Layout) const;
- uint64_t getPaddingSize(const MCSectionData *SD,
- const MCAsmLayout &Layout) const;
+ uint64_t getPaddingSize(const MCSection *SD, const MCAsmLayout &Layout) const;
bool doesSymbolRequireExternRelocation(const MCSymbol &S);
uint64_t SectionDataSize);
void WriteSection(const MCAssembler &Asm, const MCAsmLayout &Layout,
- const MCSectionData &SD, uint64_t FileOffset,
+ const MCSection &Sec, uint64_t FileOffset,
uint64_t RelocationsStart, unsigned NumRelocations);
void WriteSymtabLoadCommand(uint32_t SymbolOffset, uint32_t NumSymbols,
// to a symbol it should be passed as \p RelSymbol so that it can be updated
// afterwards. If the relocation doesn't refer to a symbol, nullptr should be
// used.
- void addRelocation(const MCSymbol *RelSymbol, const MCSectionData *SD,
+ void addRelocation(const MCSymbol *RelSymbol, const MCSection *Sec,
MachO::any_relocation_info &MRE) {
RelAndSymbol P(RelSymbol, MRE);
- Relocations[SD].push_back(P);
+ Relocations[Sec].push_back(P);
}
void RecordScatteredRelocation(const MCAssembler &Asm,
Layout.getSymbolOffset(S);
}
-uint64_t MachObjectWriter::getPaddingSize(const MCSectionData *SD,
+uint64_t MachObjectWriter::getPaddingSize(const MCSection *Sec,
const MCAsmLayout &Layout) const {
- uint64_t EndAddr =
- getSectionAddress(&SD->getSection()) + Layout.getSectionAddressSize(SD);
- unsigned Next = SD->getSection().getLayoutOrder() + 1;
+ uint64_t EndAddr = getSectionAddress(Sec) +
+ Layout.getSectionAddressSize(&Sec->getSectionData());
+ unsigned Next = Sec->getLayoutOrder() + 1;
if (Next >= Layout.getSectionOrder().size())
return 0;
void MachObjectWriter::WriteSection(const MCAssembler &Asm,
const MCAsmLayout &Layout,
- const MCSectionData &SD,
- uint64_t FileOffset,
+ const MCSection &Sec, uint64_t FileOffset,
uint64_t RelocationsStart,
unsigned NumRelocations) {
+ const MCSectionData &SD = Sec.getSectionData();
uint64_t SectionSize = Layout.getSectionAddressSize(&SD);
- const MCSectionMachO &Section = cast<MCSectionMachO>(SD.getSection());
+ const MCSectionMachO &Section = cast<MCSectionMachO>(Sec);
// The offset is unused for virtual sections.
if (Section.isVirtualSection()) {
Write32(NumRelocations ? RelocationsStart : 0);
Write32(NumRelocations);
Write32(Flags);
- Write32(IndirectSymBase.lookup(&SD)); // reserved1
+ Write32(IndirectSymBase.lookup(&SD.getSection())); // reserved1
Write32(Section.getStubSize()); // reserved2
if (is64Bit())
Write32(0); // reserved3
continue;
// Initialize the section indirect symbol base, if necessary.
- IndirectSymBase.insert(std::make_pair(it->SectionData, IndirectIndex));
+ IndirectSymBase.insert(
+ std::make_pair(&it->SectionData->getSection(), IndirectIndex));
Asm.getOrCreateSymbolData(*it->Symbol);
}
continue;
// Initialize the section indirect symbol base, if necessary.
- IndirectSymBase.insert(std::make_pair(it->SectionData, IndirectIndex));
+ IndirectSymBase.insert(
+ std::make_pair(&it->SectionData->getSection(), IndirectIndex));
// Set the symbol type to undefined lazy, but only on construction.
//
UndefinedSymbolData[i].Symbol->setIndex(Index++);
for (const MCSection &Section : Asm) {
- const MCSectionData &SD = Section.getSectionData();
- std::vector<RelAndSymbol> &Relocs = Relocations[&SD];
+ std::vector<RelAndSymbol> &Relocs = Relocations[&Section];
for (RelAndSymbol &Rel : Relocs) {
if (!Rel.Sym)
continue;
// Explicitly pad the section to match the alignment requirements of the
// following one. This is for 'gas' compatibility, it shouldn't
/// strictly be necessary.
- StartAddress += getPaddingSize(SD, Layout);
+ StartAddress += getPaddingSize(&SD->getSection(), Layout);
}
}
uint64_t Address = getSectionAddress(&*it);
uint64_t Size = Layout.getSectionAddressSize(&SD);
uint64_t FileSize = Layout.getSectionFileSize(&SD);
- FileSize += getPaddingSize(&SD, Layout);
+ FileSize += getPaddingSize(&*it, Layout);
VMSize = std::max(VMSize, Address + Size);
uint64_t RelocTableEnd = SectionDataStart + SectionDataFileSize;
for (MCAssembler::const_iterator it = Asm.begin(),
ie = Asm.end(); it != ie; ++it) {
- const MCSectionData &SD = it->getSectionData();
- std::vector<RelAndSymbol> &Relocs = Relocations[&SD];
+ std::vector<RelAndSymbol> &Relocs = Relocations[&*it];
unsigned NumRelocs = Relocs.size();
uint64_t SectionStart = SectionDataStart + getSectionAddress(&*it);
- WriteSection(Asm, Layout, SD, SectionStart, RelocTableEnd, NumRelocs);
+ WriteSection(Asm, Layout, *it, SectionStart, RelocTableEnd, NumRelocs);
RelocTableEnd += NumRelocs * sizeof(MachO::any_relocation_info);
}
const MCSectionData &SD = it->getSectionData();
Asm.writeSectionData(&SD, Layout);
- uint64_t Pad = getPaddingSize(&SD, Layout);
+ uint64_t Pad = getPaddingSize(&*it, Layout);
WriteZeros(Pad);
}
ie = Asm.end(); it != ie; ++it) {
// Write the section relocation entries, in reverse order to match 'as'
// (approximately, the exact algorithm is more complicated than this).
- std::vector<RelAndSymbol> &Relocs = Relocations[&it->getSectionData()];
+ std::vector<RelAndSymbol> &Relocs = Relocations[&*it];
for (unsigned i = 0, e = Relocs.size(); i != e; ++i) {
Write32(Relocs[e - i - 1].MRE.r_word0);
Write32(Relocs[e - i - 1].MRE.r_word1);
MachO::any_relocation_info MRE;
MRE.r_word0 = FixupOffset;
MRE.r_word1 = (IsPCRel << 24) | (Log2Size << 25) | (Type << 28);
- Writer->addRelocation(A_Base, &Fragment->getParent()->getSectionData(),
- MRE);
+ Writer->addRelocation(A_Base, Fragment->getParent(), MRE);
return;
} else if (Target.getSymA()->getKind() != MCSymbolRefExpr::VK_None ||
Target.getSymB()->getKind() != MCSymbolRefExpr::VK_None)
MachO::any_relocation_info MRE;
MRE.r_word0 = FixupOffset;
MRE.r_word1 = (IsPCRel << 24) | (Log2Size << 25) | (Type << 28);
- Writer->addRelocation(A_Base, &Fragment->getParent()->getSectionData(),
- MRE);
+ Writer->addRelocation(A_Base, Fragment->getParent(), MRE);
RelSymbol = B_Base;
Type = MachO::ARM64_RELOC_SUBTRACTOR;
MRE.r_word0 = FixupOffset;
MRE.r_word1 =
(Index << 0) | (IsPCRel << 24) | (Log2Size << 25) | (Type << 28);
- Writer->addRelocation(RelSymbol, &Fragment->getParent()->getSectionData(),
- MRE);
+ Writer->addRelocation(RelSymbol, Fragment->getParent(), MRE);
// Now set up the Addend relocation.
Type = MachO::ARM64_RELOC_ADDEND;
MRE.r_word0 = FixupOffset;
MRE.r_word1 =
(Index << 0) | (IsPCRel << 24) | (Log2Size << 25) | (Type << 28);
- Writer->addRelocation(RelSymbol, &Fragment->getParent()->getSectionData(),
- MRE);
+ Writer->addRelocation(RelSymbol, Fragment->getParent(), MRE);
}
MCObjectWriter *llvm::createAArch64MachObjectWriter(raw_pwrite_stream &OS,
(IsPCRel << 30) |
MachO::R_SCATTERED);
MRE.r_word1 = Value2;
- Writer->addRelocation(nullptr, &Fragment->getParent()->getSectionData(),
- MRE);
+ Writer->addRelocation(nullptr, Fragment->getParent(), MRE);
}
MachO::any_relocation_info MRE;
(IsPCRel << 30) |
MachO::R_SCATTERED);
MRE.r_word1 = Value;
- Writer->addRelocation(nullptr, &Fragment->getParent()->getSectionData(), MRE);
+ Writer->addRelocation(nullptr, Fragment->getParent(), MRE);
}
void ARMMachObjectWriter::RecordARMScatteredRelocation(MachObjectWriter *Writer,
(IsPCRel << 30) |
MachO::R_SCATTERED);
MRE.r_word1 = Value2;
- Writer->addRelocation(nullptr, &Fragment->getParent()->getSectionData(),
- MRE);
+ Writer->addRelocation(nullptr, Fragment->getParent(), MRE);
}
MachO::any_relocation_info MRE;
(IsPCRel << 30) |
MachO::R_SCATTERED);
MRE.r_word1 = Value;
- Writer->addRelocation(nullptr, &Fragment->getParent()->getSectionData(), MRE);
+ Writer->addRelocation(nullptr, Fragment->getParent(), MRE);
}
bool ARMMachObjectWriter::requiresExternRelocation(MachObjectWriter *Writer,
(Log2Size << 25) |
(MachO::ARM_RELOC_PAIR << 28));
- Writer->addRelocation(nullptr, &Fragment->getParent()->getSectionData(),
- MREPair);
+ Writer->addRelocation(nullptr, Fragment->getParent(), MREPair);
}
- Writer->addRelocation(RelSymbol, &Fragment->getParent()->getSectionData(),
- MRE);
+ Writer->addRelocation(RelSymbol, Fragment->getParent(), MRE);
}
MCObjectWriter *llvm::createARMMachObjectWriter(raw_pwrite_stream &OS,
MachO::any_relocation_info MRE;
makeScatteredRelocationInfo(MRE, other_half, MachO::GENERIC_RELOC_PAIR,
Log2Size, IsPCRel, Value2);
- Writer->addRelocation(nullptr, &Fragment->getParent()->getSectionData(),
- MRE);
+ Writer->addRelocation(nullptr, Fragment->getParent(), MRE);
} else {
// If the offset is more than 24-bits, it won't fit in a scattered
// relocation offset field, so we fall back to using a non-scattered
}
MachO::any_relocation_info MRE;
makeScatteredRelocationInfo(MRE, FixupOffset, Type, Log2Size, IsPCRel, Value);
- Writer->addRelocation(nullptr, &Fragment->getParent()->getSectionData(), MRE);
+ Writer->addRelocation(nullptr, Fragment->getParent(), MRE);
return true;
}
// struct relocation_info (8 bytes)
MachO::any_relocation_info MRE;
makeRelocationInfo(MRE, FixupOffset, Index, IsPCRel, Log2Size, false, Type);
- Writer->addRelocation(RelSymbol, &Fragment->getParent()->getSectionData(),
- MRE);
+ Writer->addRelocation(RelSymbol, Fragment->getParent(), MRE);
}
MCObjectWriter *llvm::createPPCMachObjectWriter(raw_pwrite_stream &OS,
MRE.r_word0 = FixupOffset;
MRE.r_word1 =
(Index << 0) | (IsPCRel << 24) | (Log2Size << 25) | (Type << 28);
- Writer->addRelocation(A_Base, &Fragment->getParent()->getSectionData(),
- MRE);
+ Writer->addRelocation(A_Base, Fragment->getParent(), MRE);
if (B_Base)
RelSymbol = B_Base;
MRE.r_word0 = FixupOffset;
MRE.r_word1 = (Index << 0) | (IsPCRel << 24) | (Log2Size << 25) |
(IsExtern << 27) | (Type << 28);
- Writer->addRelocation(RelSymbol, &Fragment->getParent()->getSectionData(),
- MRE);
+ Writer->addRelocation(RelSymbol, Fragment->getParent(), MRE);
}
bool X86MachObjectWriter::RecordScatteredRelocation(MachObjectWriter *Writer,
(IsPCRel << 30) |
MachO::R_SCATTERED);
MRE.r_word1 = Value2;
- Writer->addRelocation(nullptr, &Fragment->getParent()->getSectionData(),
- MRE);
+ Writer->addRelocation(nullptr, Fragment->getParent(), MRE);
} else {
// If the offset is more than 24-bits, it won't fit in a scattered
// relocation offset field, so we fall back to using a non-scattered
(IsPCRel << 30) |
MachO::R_SCATTERED);
MRE.r_word1 = Value;
- Writer->addRelocation(nullptr, &Fragment->getParent()->getSectionData(), MRE);
+ Writer->addRelocation(nullptr, Fragment->getParent(), MRE);
return true;
}
MRE.r_word0 = Value;
MRE.r_word1 =
(IsPCRel << 24) | (Log2Size << 25) | (MachO::GENERIC_RELOC_TLV << 28);
- Writer->addRelocation(&Target.getSymA()->getSymbol(),
- &Fragment->getParent()->getSectionData(), MRE);
+ Writer->addRelocation(&Target.getSymA()->getSymbol(), Fragment->getParent(),
+ MRE);
}
void X86MachObjectWriter::RecordX86Relocation(MachObjectWriter *Writer,
MRE.r_word0 = FixupOffset;
MRE.r_word1 =
(Index << 0) | (IsPCRel << 24) | (Log2Size << 25) | (Type << 28);
- Writer->addRelocation(RelSymbol, &Fragment->getParent()->getSectionData(),
- MRE);
+ Writer->addRelocation(RelSymbol, Fragment->getParent(), MRE);
}
MCObjectWriter *llvm::createX86MachObjectWriter(raw_pwrite_stream &OS,