ARM: mvebu: support running big-endian

Add indication we can run these cores in BE mode, and ensure that the
secondary CPU is set to big-endian mode in the initialisation code as
the initial code runs little-endian.

Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Jason Cooper <jason@lakedaemon.net>
(cherry picked from commit bca028e7c2537fea9f401c20dd7b2103358b5efe)

Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
Conflicts:
	arch/arm/mach-mvebu/headsmp.S

diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index 80a8bcacd9d539c0a684e3beaa927b07dd720566..317cdb80009958236d8c3300142a22c0ae0c61e3 100644 (file)
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -1,5 +1,6 @@
 config ARCH_MVEBU
        bool "Marvell SOCs with Device Tree support" if ARCH_MULTI_V7
+       select ARCH_SUPPORTS_BIG_ENDIAN
        select CLKSRC_MMIO
        select COMMON_CLK
        select GENERIC_CLOCKEVENTS

diff --git a/arch/arm/mach-mvebu/coherency_ll.S b/arch/arm/mach-mvebu/coherency_ll.S
index 5476669ba9056ff80d63fab31d8f266ef25a2652..ee7598fe75db873dc81843610939d189969833a3 100644 (file)
--- a/arch/arm/mach-mvebu/coherency_ll.S
+++ b/arch/arm/mach-mvebu/coherency_ll.S
@@ -20,6 +20,8 @@
 #define ARMADA_XP_CFB_CTL_REG_OFFSET 0x0
 #define ARMADA_XP_CFB_CFG_REG_OFFSET 0x4
 
+#include <asm/assembler.h>
+
        .text
 /*
  * r0: Coherency fabric base register address
@@ -29,6 +31,7 @@ ENTRY(ll_set_cpu_coherent)
        /* Create bit by cpu index */
        mov     r3, #(1 << 24)
        lsl     r1, r3, r1
+ARM_BE8(rev    r1, r1)
 
        /* Add CPU to SMP group - Atomic */
        add     r3, r0, #ARMADA_XP_CFB_CTL_REG_OFFSET

diff --git a/arch/arm/mach-mvebu/headsmp.S b/arch/arm/mach-mvebu/headsmp.S
index a06e0ede8c0897177566ffb22b76c7218b64d15a..458ed3fb26268c312604f3b98cbf7d3560625f60 100644 (file)
--- a/arch/arm/mach-mvebu/headsmp.S
+++ b/arch/arm/mach-mvebu/headsmp.S
@@ -21,6 +21,8 @@
 #include <linux/linkage.h>
 #include <linux/init.h>
 
+#include <asm/assembler.h>
+
 /*
  * At this stage the secondary CPUs don't have acces yet to the MMU, so
  * we have to provide physical addresses
@@ -35,6 +37,7 @@
  * startup
  */
 ENTRY(armada_xp_secondary_startup)
+ ARM_BE8(setend        be )                    @ go BE8 if entered LE
 
        /* Read CPU id */
        mrc     p15, 0, r1, c0, c0, 5