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drm/i915/crt: Flush register prior to waiting for vblank.
author
Chris Wilson
<chris@chris-wilson.co.uk>
Mon, 9 Aug 2010 13:50:53 +0000
(14:50 +0100)
committer
Chris Wilson
<chris@chris-wilson.co.uk>
Wed, 8 Sep 2010 09:13:31 +0000
(10:13 +0100)
If we don't flush the write then we can not be sure that the border
colour will have taken effect by the time we try to read it back.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
drivers/gpu/drm/i915/intel_crt.c
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diff --git
a/drivers/gpu/drm/i915/intel_crt.c
b/drivers/gpu/drm/i915/intel_crt.c
index c2982e48b61f97a94b1e0431d26670fc64dd32f7..626279791b892333a823c536818a006afa5711e1 100644
(file)
--- a/
drivers/gpu/drm/i915/intel_crt.c
+++ b/
drivers/gpu/drm/i915/intel_crt.c
@@
-327,6
+327,7
@@
intel_crt_load_detect(struct drm_crtc *crtc, struct intel_encoder *intel_encoder
if (IS_I9XX(dev)) {
uint32_t pipeconf = I915_READ(pipeconf_reg);
I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER);
+ POSTING_READ(pipeconf_reg);
/* Wait for next Vblank to substitue
* border color for Color info */
intel_wait_for_vblank(dev, pipe);