Add TargetRegisterClass::getSuperRegIndices().

This is a pointer into one of the tables used by
getMatchingSuperRegClass(). It makes it possible to use a shared
implementation of that function.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156121 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/include/llvm/Target/TargetRegisterInfo.h b/include/llvm/Target/TargetRegisterInfo.h
index dd8044dd850e016d342462c7b290296df29ce8b3..85562b60100f2c95d12be27d732fc8509d1ad9af 100644 (file)
--- a/include/llvm/Target/TargetRegisterInfo.h
+++ b/include/llvm/Target/TargetRegisterInfo.h
@@ -43,6 +43,7 @@ public:
   const MCRegisterClass *MC;
   const vt_iterator VTs;
   const uint32_t *SubClassMask;
+  const uint16_t *SuperRegIndices;
   const sc_iterator SuperClasses;
   const sc_iterator SuperRegClasses;
   ArrayRef<uint16_t> (*OrderFunc)(const MachineFunction&);
@@ -163,6 +164,18 @@ public:
     return SubClassMask;
   }
 
+  /// getSuperRegIndices - Returns a 0-terminated list of sub-register indices
+  /// that projec some super-register class into this register class. The list
+  /// has an entry for each Idx such that:
+  ///
+  ///   There exists SuperRC where:
+  ///     For all Reg in SuperRC:
+  ///       this->contains(Reg:Idx)
+  ///
+  const uint16_t *getSuperRegIndices() const {
+    return SuperRegIndices;
+  }
+
   /// getSuperClasses - Returns a NULL terminated list of super-classes.  The
   /// classes are ordered by ID which is also a topological ordering from large
   /// to small classes.  The list does NOT include the current class.

diff --git a/utils/TableGen/RegisterInfoEmitter.cpp b/utils/TableGen/RegisterInfoEmitter.cpp
index 48bcca706a671a0363dc3f9eae2e1bf8deb66794..6769892db42ac6c73b5ba035fd2599aae9a6f18a 100644 (file)
--- a/utils/TableGen/RegisterInfoEmitter.cpp
+++ b/utils/TableGen/RegisterInfoEmitter.cpp
@@ -845,7 +845,7 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
     //
     // The 0-terminated list of subreg indices starts at:
     //
-    //   SuperRegIdxSeqs + SuperRegIdxOffset[RC]
+    //   RC->getSuperRegIndices() = SuperRegIdxSeqs + ...
     //
     // The corresponding bitmasks follow the sub-class mask in memory. Each
     // mask has RCMaskWords uint32_t entries.
@@ -946,7 +946,8 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
          << '&' << Target.getName() << "MCRegisterClasses[" << RC.getName()
          << "RegClassID],\n    "
          << "VTLists + " << VTSeqs.get(RC.VTs) << ",\n    "
-         << RC.getName() << "SubClassMask,\n    ";
+         << RC.getName() << "SubClassMask,\n    SuperRegIdxSeqs + "
+         << SuperRegIdxSeqs.get(SuperRegIdxLists[i]) << ",\n    ";
       if (RC.getSuperClasses().empty())
         OS << "NullRegClasses,\n    ";
       else
@@ -1062,8 +1063,7 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
        << "  assert(A && B && \"Missing regclass\");\n"
        << "  assert(Idx && Idx <= " << SubRegIndices.size()
        << " && \"Bad subreg\");\n"
-       << "  const uint16_t *SRI = SuperRegIdxSeqs + "
-          "SuperRegIdxOffset[B->getID()];\n"
+       << "  const uint16_t *SRI = B->getSuperRegIndices();\n"
        << "  unsigned Offset = 0;\n"
        << "  while (SRI[Offset] != Idx) {\n"
        << "    if (!SRI[Offset])\n      return 0;\n"