[mips] Added support for the ERETNC instruction.

Summary: This required adding the instruction predicate HasMips32r5.

Patch by Scott Egerton.

Reviewers: dsanders, vkalintiris

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11136

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242666 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/Mips/MipsInstrFormats.td b/lib/Target/Mips/MipsInstrFormats.td
index 5f4fcc354616b6bcac65ce48ad0c8f6b5df9a9fc..73886689b3e88540b0bc780d722fd735fdb14a8a 100644 (file)
--- a/lib/Target/Mips/MipsInstrFormats.td
+++ b/lib/Target/Mips/MipsInstrFormats.td
@@ -644,16 +644,16 @@ class BRK_FM<bits<6> funct> : StdArch
 //  Exception return format <Cop0|1|0|funct>
 //===----------------------------------------------------------------------===//
 
-class ER_FM<bits<6> funct> : StdArch
+class ER_FM<bits<6> funct, bit LLBit> : StdArch
 {
   bits<32> Inst;
   let Inst{31-26} = 0x10;
   let Inst{25}    = 1;
-  let Inst{24-6}  = 0;
+  let Inst{24-7}  = 0;
+  let Inst{6} = LLBit;
   let Inst{5-0}   = funct;
 }
 
-
 //===----------------------------------------------------------------------===//
 //  Enable/disable interrupt instruction format <Cop0|MFMC0|rt|12|0|sc|0|0>
 //===----------------------------------------------------------------------===//

diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td
index ab98c9054e74713d28571577ae820c2d31ec6965..0862285941fa436339346ffb3b8ab3642b158c12 100644 (file)
--- a/lib/Target/Mips/MipsInstrInfo.td
+++ b/lib/Target/Mips/MipsInstrInfo.td
@@ -166,6 +166,8 @@ def HasMips32    :    Predicate<"Subtarget->hasMips32()">,
                       AssemblerPredicate<"FeatureMips32">;
 def HasMips32r2  :    Predicate<"Subtarget->hasMips32r2()">,
                       AssemblerPredicate<"FeatureMips32r2">;
+def HasMips32r5  :    Predicate<"Subtarget->hasMips32r5()">,
+                      AssemblerPredicate<"FeatureMips32r5">;
 def HasMips32r6  :    Predicate<"Subtarget->hasMips32r6()">,
                       AssemblerPredicate<"FeatureMips32r6">;
 def NotMips32r6  :    Predicate<"!Subtarget->hasMips32r6()">,
@@ -242,6 +244,7 @@ class ISA_MIPS32R2 { list<Predicate> InsnPredicates = [HasMips32r2]; }
 class ISA_MIPS32R2_NOT_32R6_64R6 {
   list<Predicate> InsnPredicates = [HasMips32r2, NotMips32r6, NotMips64r6];
 }
+class ISA_MIPS32R5 { list<Predicate> InsnPredicates = [HasMips32r5]; }
 class ISA_MIPS64   { list<Predicate> InsnPredicates = [HasMips64]; }
 class ISA_MIPS64_NOT_64R6 {
   list<Predicate> InsnPredicates = [HasMips64, NotMips64r6];
@@ -1290,9 +1293,10 @@ def TRAP : TrapBase<BREAK>;
 def SDBBP : MMRel, SYS_FT<"sdbbp">, SDBBP_FM, ISA_MIPS32_NOT_32R6_64R6;
 
 let AdditionalPredicates = [NotInMicroMips] in {
-def ERET : MMRel, ER_FT<"eret">, ER_FM<0x18>, INSN_MIPS3_32;
+def ERET : MMRel, ER_FT<"eret">, ER_FM<0x18, 0x0>, INSN_MIPS3_32;
+def ERETNC : MMRel, ER_FT<"eretnc">, ER_FM<0x18, 0x1>, ISA_MIPS32R5;
 }
-def DERET : MMRel, ER_FT<"deret">, ER_FM<0x1f>, ISA_MIPS32;
+def DERET : MMRel, ER_FT<"deret">, ER_FM<0x1f, 0x0>, ISA_MIPS32;
 
 let AdditionalPredicates = [NotInMicroMips] in {
 def EI : MMRel, StdMMR6Rel, DEI_FT<"ei", GPR32Opnd>, EI_FM<1>, ISA_MIPS32R2;

diff --git a/lib/Target/Mips/MipsSubtarget.h b/lib/Target/Mips/MipsSubtarget.h
index 1db8881404c987e127b716bb00fec3a4cfc69377..1e3a808d963e51d6ad317fd1b8f8f2601615a854 100644 (file)
--- a/lib/Target/Mips/MipsSubtarget.h
+++ b/lib/Target/Mips/MipsSubtarget.h
@@ -189,7 +189,7 @@ public:
   }
   bool hasMips32r5() const {
     return (MipsArchVersion >= Mips32r5 && MipsArchVersion < Mips32Max) ||
-           hasMips64r2();
+           hasMips64r5();
   }
   bool hasMips32r6() const {
     return (MipsArchVersion >= Mips32r6 && MipsArchVersion < Mips32Max) ||

diff --git a/test/MC/Disassembler/Mips/mips32r5/valid-mips32r5.txt b/test/MC/Disassembler/Mips/mips32r5/valid-mips32r5.txt
index 282f3a2b0544073c4db315220d809c3c52a4459d..0593fda2111274385a8f4a3123ba006aba6399c4 100644 (file)
--- a/test/MC/Disassembler/Mips/mips32r5/valid-mips32r5.txt
+++ b/test/MC/Disassembler/Mips/mips32r5/valid-mips32r5.txt
@@ -88,6 +88,7 @@
 0x46 0x07 0x30 0x3d # CHECK: c.nge.s $f6, $f7
 0x46 0x07 0x30 0x3e # CHECK: c.le.s $f6, $f7
 0x46 0x07 0x30 0x3f # CHECK: c.ngt.s $f6, $f7
+0x42 0x00 0x00 0x58 # CHECK: eretnc
 0x46 0x07 0x32 0x40 # CHECK: add.s $f9, $f6, $f7
 0x46 0x07 0x32 0x41 # CHECK: sub.s $f9, $f6, $f7
 0x46 0x07 0x32 0x42 # CHECK: mul.s $f9, $f6, $f7

diff --git a/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt b/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt
index e1721b93483573e3fc6cc8546b2471c2bd2374d9..2791b7af58fe696c77ee8b80f9d6cb5232c7d001 100644 (file)
--- a/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt
+++ b/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt
@@ -126,6 +126,7 @@
 0x46 0xa4 0x18 0x8d # CHECK: cmp.sult.d $f2, $f3, $f4
 0x46 0xa4 0x18 0x8e # CHECK: cmp.sle.d $f2, $f3, $f4
 0x46 0xa4 0x18 0x8f # CHECK: cmp.sule.d $f2, $f3, $f4
+0x42 0x00 0x00 0x58 # CHECK: eretnc
 # FIXME: The encode/decode functions are not inverses of each other.
 #        The immediate should be 8 but the disassembler currently emits 12
 0x49 0x20 0x00 0x02 # CHECK: bc2eqz $0, 12

diff --git a/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5.txt b/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5.txt
index 1b30144acab472eaa31aaabdebc7e30866f9c795..a27fa98c96317cad52ba45c5b8c9f1268501e14c 100644 (file)
--- a/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5.txt
+++ b/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5.txt
@@ -165,6 +165,7 @@
 0x46 0x2e 0x60 0x3d # CHECK: c.nge.d $f12, $f14
 0x46 0x2e 0x60 0x3e # CHECK: c.le.d $f12, $f14
 0x46 0x2e 0x60 0x3f # CHECK: c.ngt.d $f12, $f14
+0x42 0x00 0x00 0x58 # CHECK: eretnc
 0x46 0x2e 0x62 0x00 # CHECK: add.d $f8, $f12, $f14
 0x46 0x2e 0x62 0x01 # CHECK: sub.d $f8, $f12, $f14
 0x46 0x2e 0x62 0x02 # CHECK: mul.d $f8, $f12, $f14

diff --git a/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt b/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt
index 45379d9c8988a5e238a6f8e83bdb03a3d41d766c..5be21256d28685e17810a980c6f0829bc7bfaaee 100644 (file)
--- a/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt
+++ b/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt
@@ -143,6 +143,7 @@
 0x46 0xa4 0x18 0x8d # CHECK: cmp.sult.d $f2, $f3, $f4
 0x46 0xa4 0x18 0x8e # CHECK: cmp.sle.d $f2, $f3, $f4
 0x46 0xa4 0x18 0x8f # CHECK: cmp.sule.d $f2, $f3, $f4
+0x42 0x00 0x00 0x58 # CHECK: eretnc
 # FIXME: The encode/decode functions are not inverses of each other.
 #        The immediate should be 8 but the disassembler currently emits 12
 0x49 0x20 0x00 0x02 # CHECK: bc2eqz $0, 12

diff --git a/test/MC/Mips/mips32r5/invalid-mips32.s b/test/MC/Mips/mips32r5/invalid-mips32.s
new file mode 100644 (file)
index 0000000..fc1a516
--- /dev/null
+++ b/test/MC/Mips/mips32r5/invalid-mips32.s
@@ -0,0 +1,8 @@
+# Instructions that are invalid
+#
+# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32 \
+# RUN:     2>%t1
+# RUN: FileCheck %s < %t1
+
+       .set noat
+        eretnc                      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled

diff --git a/test/MC/Mips/mips32r5/invalid-mips32r2.s b/test/MC/Mips/mips32r5/invalid-mips32r2.s
new file mode 100644 (file)
index 0000000..2e7a297
--- /dev/null
+++ b/test/MC/Mips/mips32r5/invalid-mips32r2.s
@@ -0,0 +1,8 @@
+# Instructions that are invalid
+#
+# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r2 \
+# RUN:     2>%t1
+# RUN: FileCheck %s < %t1
+
+       .set noat
+        eretnc                      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled

diff --git a/test/MC/Mips/mips32r5/invalid-mips32r3.s b/test/MC/Mips/mips32r5/invalid-mips32r3.s
new file mode 100644 (file)
index 0000000..3ee188f
--- /dev/null
+++ b/test/MC/Mips/mips32r5/invalid-mips32r3.s
@@ -0,0 +1,8 @@
+# Instructions that are invalid
+#
+# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r3 \
+# RUN:     2>%t1
+# RUN: FileCheck %s < %t1
+
+       .set noat
+        eretnc                      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled

diff --git a/test/MC/Mips/mips32r5/valid.s b/test/MC/Mips/mips32r5/valid.s
index f12d75113203cdc92fbd576991007eead8de2f93..3bb8e84ffe0fb262aefe72991a5ff52c4fd704c4 100644 (file)
--- a/test/MC/Mips/mips32r5/valid.s
+++ b/test/MC/Mips/mips32r5/valid.s
@@ -70,6 +70,7 @@ a:
         ei        $14                  # CHECK: ei  $14       # encoding: [0x41,0x6e,0x60,0x20]
         ei                             # CHECK: ei            # encoding: [0x41,0x60,0x60,0x20]
         eret
+        eretnc                         # CHECK: eretnc        # encoding: [0x42,0x00,0x00,0x58]
         floor.w.d $f14,$f11
         floor.w.s $f8,$f9
         j         1f                   # CHECK: j $tmp0 # encoding: [0b000010AA,A,A,A]

diff --git a/test/MC/Mips/mips32r6/valid.s b/test/MC/Mips/mips32r6/valid.s
index 52752c5a6997e5285bc1a3d13e46bbeb11c416d4..073da85dfde944d06c4d0a2bcafebb681cea5dc5 100644 (file)
--- a/test/MC/Mips/mips32r6/valid.s
+++ b/test/MC/Mips/mips32r6/valid.s
@@ -103,6 +103,8 @@ a:
         divu    $2,$3,$4         # CHECK: divu $2, $3, $4  # encoding: [0x00,0x64,0x10,0x9b]
         ei      $14              # CHECK: ei  $14          # encoding: [0x41,0x6e,0x60,0x20]
         ei                       # CHECK: ei               # encoding: [0x41,0x60,0x60,0x20]
+        eret
+        eretnc                   # CHECK: eretnc           # encoding: [0x42,0x00,0x00,0x58]
         jialc   $5, 256          # CHECK: jialc $5, 256    # encoding: [0xf8,0x05,0x01,0x00]
         jic     $5, 256          # CHECK: jic $5, 256      # encoding: [0xd8,0x05,0x01,0x00]
         lsa     $2, $3, $4, 3    # CHECK: lsa  $2, $3, $4, 3 # encoding: [0x00,0x64,0x10,0xc5]

diff --git a/test/MC/Mips/mips64r5/invalid-mips64.s b/test/MC/Mips/mips64r5/invalid-mips64.s
new file mode 100644 (file)
index 0000000..412fb31
--- /dev/null
+++ b/test/MC/Mips/mips64r5/invalid-mips64.s
@@ -0,0 +1,8 @@
+# Instructions that are invalid
+#
+# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips64 \
+# RUN:     2>%t1
+# RUN: FileCheck %s < %t1
+
+       .set noat
+        eretnc                      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled

diff --git a/test/MC/Mips/mips64r5/invalid-mips64r2.s b/test/MC/Mips/mips64r5/invalid-mips64r2.s
new file mode 100644 (file)
index 0000000..1ee1594
--- /dev/null
+++ b/test/MC/Mips/mips64r5/invalid-mips64r2.s
@@ -0,0 +1,8 @@
+# Instructions that are invalid
+#
+# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips64r2 \
+# RUN:     2>%t1
+# RUN: FileCheck %s < %t1
+
+       .set noat
+        eretnc                      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled

diff --git a/test/MC/Mips/mips64r5/invalid-mips64r3.s b/test/MC/Mips/mips64r5/invalid-mips64r3.s
new file mode 100644 (file)
index 0000000..e80d7a1
--- /dev/null
+++ b/test/MC/Mips/mips64r5/invalid-mips64r3.s
@@ -0,0 +1,8 @@
+# Instructions that are invalid
+#
+# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips64r3 \
+# RUN:     2>%t1
+# RUN: FileCheck %s < %t1
+
+       .set noat
+        eretnc                      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled

diff --git a/test/MC/Mips/mips64r5/valid.s b/test/MC/Mips/mips64r5/valid.s
index d4e52dcca67e799ac64a7da40d79c0f7f50c544c..c570b3e24aac3a2bef6cdeeed77744db8dbed86b 100644 (file)
--- a/test/MC/Mips/mips64r5/valid.s
+++ b/test/MC/Mips/mips64r5/valid.s
@@ -132,6 +132,7 @@ a:
         ei        $14                  # CHECK: ei  $14       # encoding: [0x41,0x6e,0x60,0x20]
         ei                             # CHECK: ei            # encoding: [0x41,0x60,0x60,0x20]
         eret
+        eretnc                         # CHECK: eretnc        # encoding: [0x42,0x00,0x00,0x58]
         floor.l.d $f26,$f7
         floor.l.s $f12,$f5
         floor.w.d $f14,$f11

diff --git a/test/MC/Mips/mips64r6/valid.s b/test/MC/Mips/mips64r6/valid.s
index 3dc771a80d54d178425dfaf5c7d93959ce2efe18..6249d51781c5f285969eebd747b7f6a1bac6be7e 100644 (file)
--- a/test/MC/Mips/mips64r6/valid.s
+++ b/test/MC/Mips/mips64r6/valid.s
@@ -132,6 +132,7 @@ a:
         dsubu   $15,$11,5025     # CHECK: daddiu $15, $11, -5025 # encoding: [0x65,0x6f,0xec,0x5f]
         ei                       # CHECK: ei               # encoding: [0x41,0x60,0x60,0x20]
         ei      $14              # CHECK: ei  $14          # encoding: [0x41,0x6e,0x60,0x20]
+        eretnc                   # CHECK: eretnc                 # encoding: [0x42,0x00,0x00,0x58]
         j       1f               # CHECK: j $tmp0                # encoding: [0b000010AA,A,A,A]
                                  # CHECK:                        #   fixup A - offset: 0, value: ($tmp0), kind: fixup_Mips_26
         j       a                # CHECK: j a                    # encoding: [0b000010AA,A,A,A]